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the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. document no. u13216ej1v0pm00 (1st edition) date published march 1998 j cp(k) printed in japan 1998 8-bit single-chip microcontroller preliminary product information mos integrated circuit m m m m pd789166y,789167y,789176y,789177y the m m m m pd789166y, m m m m pd789167y, m m m m pd789176y, and m m m m PD789177Y are m m m m pd789167y and m m m m PD789177Y sub-series products of the 78k/0s series. these microcontrollers feature an 8-bit cpu, i/o ports, timers, a serial interface, a/d converters, and interrupt control circuits. in addition, a flash memory product ( m pd78f9177y) that can operate within the same voltage range as the masked rom models, and a range of related development tools are being developed. the functions of these microcontrollers are described in the following users manuals. refer to these manuals when designing a system based on any of these microcontrollers. m m m m PD789177Y sub-series users manual : to be created 78k/0s series users manual, instruction : u11047e features ? rom and ram sizes item program memory data memory product name rom internal high-speed ram m pd789166y 16 kbytes 512 8 bits m pd789167y 24 kbytes m pd789176y 16 kbytes m PD789177Y 24 kbytes ? variable minimum instruction execution time: from high-speed (0.4 m s: with the main system clock running at 5.0 mhz) to very low-speed (122 m s: with the subsystem clock running at 32.768 khz) ? eight a/d converters with 8-bit resolution (for m pd789166y and m pd789167y) ? eight a/d converters with an 10-bit resolution (for m pd789176y and m PD789177Y) ? 31 i/o ports ? two serial interface channels: ? switchable between three-wire serial i/o and uart modes ? system management bus (smb) ? six timers: ? 16-bit timer counter ? three 8-bit timer/event counters ? clock timer ? watchdog timer ? 16-bit multiplier ? power supply voltage: v dd = 1.8 to 5.5 v
u13216ej1v0x100 july 1998 ns cp(k) supplement [document name] m pd789166y, 789167y, 789176y, 789177y preliminary product information [document no., date published] u13216ej1v0pm00 (1st edition), march 1998 j cp(k) before change after change m pd789167y,789177y subseries m pd789167,789177 subseries m pd789166y, 789167y m pd789166, 789167 m pd789176y, 789177y m pd789176, 789177 product name m pd78f9177y m pd78f9177 package 42-pin plastic shrink dip 44-pin plastic qfp 48-pin plastic tqfp 44-pin plastic qfp m pd789166ygb-xxx-3bs m pd789166gb-xxx-3bs-mtx m pd789167ygb-xxx-3bs m pd789167gb-xxx-3bs-mtx m pd789176ygb-xxx-3bs m pd789176gb-xxx-3bs-mtx m PD789177Ygb-xxx-3bs m pd789177gb-xxx-3bs-mtx part number m pd78f9177ygb-3bs m pd78f9177gb-3bs-mtx smb on chip not provided
preliminary product information 2 m m m m pd789166y, 789167y, 789176y, 789177y applications power windows, keyless entries, battery management units, side air bags, etc. ordering information part number package m pd789166ycu- 42-pin plastic shrink dip (600 mil) m pd789166ygb- -3bs 44-pin plastic qfp (10 10 mm) m pd789166yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7 mm) m pd789167ycu- 42-pin plastic shrink dip (600 mil) m pd789167ygb- -3bs 44-pin plastic qfp (10 10 mm) m pd789167yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7 mm) m pd789176ycu- 42-pin plastic shrink dip (600 mil) m pd789176ygb- -3bs 44-pin plastic qfp (10 10 mm) m pd789176yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7 mm) m PD789177Ycu- 42-pin plastic shrink dip (600 mil) m PD789177Ygb- -3bs 44-pin plastic qfp (10 10 mm) m PD789177Yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7 mm) remark indicates rom code suffix.
preliminary product information 3 m m m m pd789166y, 789167y, 789176y, 789177y 78k/0s series development the 78k/0s series products are shown below. the sub-series names are indicated in frames. under development 42/44-pin for small-scale, general- purpose applications 28-pin 78k/0s series 80-pin 80-pin 42/44-pin 5-pin pd789026 m m for lcd driving pd789417 m device developed by enhancing the a/d function of the pd789407 device developed by adding the a/d function and enhancing the timers of the pd789026 pd789407 m for assp pd789800 m device for a pc keyboard, with a built-in usb function device for an ic card, with a built-in security circuit pd789810 m in production for small-scale, general-purpose applications and a/d function pd789114 m pd789104 m pd789134 m pd789124 m 28/30-pin 28/30-pin 28/30-pin 28/30-pin rc oscillator version of the pd789197y pd789014 m PD789177Y m pd789167y m pd789197y m 42/44/48-pin 42/44/48-pin 44/48-pin pd789217y m 44/48-pin device developed by enhancing the timers of the pd789014 and expanding rom and ram. with built-in uart bus and capable of low-voltage (1.8 v) operation m with built-in eeprom tm in the PD789177Y device developed by enhancing the a/d function of the pd789167y device developed by enhancing the timers of the pd789104, with a built-in smb device developed by enhancing the a/d function of the pd789124 rc oscillator version of the pd789104 device developed by enhancing the a/d function of the pd789104 device developed by adding the a/d function and multiplier to the pd789014 m m m m m m m m m
preliminary product information 4 m m m m pd789166y, 789167y, 789176y, 789177y the following table lists the major differences in functions between the sub-series. function timer 8-bit 10-bit serial minimum sub-series 8-bit 16-bit clock wdt a/d a/d interface v dd value m pd789026 4 k-16 k 1 ch 1 ch - 1 ch -- 1 ch (uart: 1 ch) 34 pins 1.8 v - m pd789014 2 k-4 k 2 ch - 22 pins m pd789217y 16 k-24 k 3 ch 1 ch 1 ch 1 ch - 8 ch 2 ch uart : 1 ch smb : 1 ch 31 pins 1.8 v rc-oscillator version, with built-in eeprom m pd789197y with built-in eeprom m PD789177Y - m pd789167y 8 ch - m pd789134 2 k-8 k 1 ch -- 4 ch 1 ch (uart: 1 ch) 20 pins m pd789124 4 ch - m pd789114 - 4 ch - m pd789104 4 ch - lcd driving m pd789417 12 k-24 k 3 ch 1 ch 1 ch 1 ch - 7 ch 1 ch (uart: 1 ch) 43 pins 1.8 v - m pd789407 7 ch - assp m pd789800 8 k 2 ch -- 1 ch -- 2 ch (usb: 1 ch) 31 pins 4.0 v - m pd789810 6 k -- 1 pin 1.8 v with built-in eeprom small-scale, general purpose applications small-scale, general- purpose applications and a/d function rom size remarks i/o rc-oscillator version
preliminary product information 5 m m m m pd789166y, 789167y, 789176y, 789177y functions product m pd789166y m pd789167y m pd789176y m PD789177Y item internal memory rom 16 kbytes 24 kbytes 16 kbytes 24 kbytes high-speed ram 512 bytes minimum instruction execution time ? 0.4/1.6 m s (operation with main system clock (ceramic/crystal oscillation) running at 5.0 mhz) ? 122 m s (operation with subsystem clock running at 32.768 khz). general-purpose registers 8 bits 8 registers instruction set ? 16-bit operations ? bit manipulations (such as set, reset, and test) multiplier 8 bits 8 bits = 16 bits i/o ports total of 31 port pins ? 8 cmos input pins ? 17 cmos input/output pins ? 6 n-channel open-drain pins a/d converters eight channels with 8-bit resolution eight channels with 10-bit resolution serial interface ? switchable between three-wire serial i/o and uart modes ? system management bus (smb) timers ? 16-bit timer counter ? three 8-bit timer/event counters ? clock timer ? watchdog timer timer output four outputs buzzer output one output vectored interrupt maskable 12 internal and 4 external interrupts sources nonmaskable internal interrupt power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = - 40c to + 85c package 42-pin plastic shrink dip (600 mil) 44-pin plastic qfp (10 10 mm) 48-pin plastic tqfp (fine pitch) (7 7 mm)
preliminary product information 6 m m m m pd789166y, 789167y, 789176y, 789177y contents 1. pin configuration (top view) ................................................................................................. 8 2. block diagram ................................................................................................................ ............. 12 3. pin functions ................................................................................................................ ................ 13 3.1 port pins ................................................................................................................... ............................... 13 3.2 non-port pins............................................................................................................... ........................... 14 3.3 pin input/output circuits and handling of unused pins .................................................................... 15 4. cpu architecture ............................................................................................................. .......... 17 4.1 memory space ................................................................................................................ ........................ 17 4.2 data memory addressing ...................................................................................................... ................ 18 4.3 processor registers......................................................................................................... ...................... 19 5. peripheral hardware functions ........................................................................................ 24 5.1 ports ....................................................................................................................... ................................. 24 5.2 clock generator............................................................................................................. ......................... 31 5.3 16-bit timer counter ........................................................................................................ ...................... 36 5.4 8-bit timer/event counter ................................................................................................... .................. 43 5.5 clock timer ................................................................................................................. ............................ 50 5.6 watchdog timer .............................................................................................................. ....................... 53 5.7 a/d converter............................................................................................................... ........................... 57 5.8 serial interface............................................................................................................ ............................ 62 5.9 multiplier.................................................................................................................. ................................ 91 6. interrupt functions .......................................................................................................... ....... 94 6.1 interrupt function types .................................................................................................... ................... 94 6.2 interrupt sources and configuration......................................................................................... ........... 94 6.3 interrupt function control registers........................................................................................ ............ 97 7. standby function ............................................................................................................. .......... 103 7.1 standby function ............................................................................................................ ....................... 103 7.2 standby function control register ........................................................................................... ........... 106 8. reset functions .............................................................................................................. ............ 107 9. mask options ................................................................................................................. ............... 110 10. instruction set overview .................................................................................................... ... 111 10.1 legend..................................................................................................................... ................................ 111 10.2 operations................................................................................................................. .............................. 113
preliminary product information 7 m m m m pd789166y, 789167y, 789176y, 789177y 11. electrical characteristics.................................................................................................. 118 12. package drawings ............................................................................................................ ......... 133 appendix a development tools................................................................................................. 136 appendix b related documents ................................................................................................ 1 38
preliminary product information 8 m m m m pd789166y, 789167y, 789176y, 789177y 1. pin configuration (top view) ? 42-pin plastic shrink dip (600 mil) m pd789166ycu- m pd789167ycu- m pd789176ycu- m PD789177Ycu- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p50 p05 p04 p03 p02 p01 p00 p26/to80 p25/ti80/ss20 v dd v ss x1 x2 reset xt1 xt2 ic p24/sda0 p23/scl0 p22/si20/r x d20 p21/so20/t x d20 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p51 p52 p53 av dd av ref p60/ani0 p61/ani1 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 p67/ani7 av ss p10 p11 p30/intp0/ti81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 p20/sck20/asck20 cautions 1. connect the ic (internally connected) pin directly to the v ss pin. 2. connect the av dd pin to the v dd pin. 3. connect the av ss pin to the v ss pin.
preliminary product information 9 m m m m pd789166y, 789167y, 789176y, 789177y ? 44-pin plastic qfp (10 10 mm) m pd789166ygb- -3bs m pd789167ygb- -3bs m pd789176ygb- -3bs m PD789177Ygb- -3bs p60/ani0 p61/ani1 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 p67/ani7 av ss p10 p11 33 32 31 30 29 28 27 26 25 24 23 p01 p00 p26/to80 p25/ti80/ss20 v dd v ss x1 x2 reset xt1 xt2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 av ref av dd p53 p52 p51 p50 p05 nc p04 p03 p02 p30/intp0/ti81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 p20/sck20/asck20 nc p21/so20/t x d20 p22/si20/r x d20 p23/scl0 p24/sda0 ic cautions 1. connect the ic (internally connected) pin directly to the v ss pin. 2. connect the av dd pin to the v dd pin. 3. connect the av ss pin to the v ss pin.
preliminary product information 10 m m m m pd789166y, 789167y, 789176y, 789177y ? 48-pin plastic tqfp (fine pitch) (7 7 mm) m pd789166yga- -9eu m pd789167yga- -9eu m pd789176yga- -9eu m PD789177Yga- -9eu p60/ani0 p61/ani1 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 p67/ani7 av ss p10 p11 nc 36 35 34 33 32 31 30 29 28 27 26 25 p01 p00 p26/to80 p25/ti80/ss20 v dd nc v ss x1 x2 reset xt1 xt2 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 av ref av dd p53 p52 nc p51 p50 p05 nc p04 p03 p02 p30/intp0/ti81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 p20/sck20/asck20 nc nc p21/so20/t x d20 p22/si20/r x d20 p23/scl0 p24/sda0 ic 24 cautions 1. connect the ic (internally connected) pin directly to the v ss pin. 2. connect the av dd pin to the v dd pin. 3. connect the av ss pin to the v ss pin.
preliminary product information 11 m m m m pd789166y, 789167y, 789176y, 789177y ani0-ani7 : analog input reset : reset asck20 : asynchronous serial input rxd20 : receive data av dd : analog power supply sck20 : serial clock (for sio20) av ref : analog reference voltage scl0 : serial clock (for smb0) av ss : analog ground sda0 : serial data bzo90 : buzzer output si20 : serial input cpt90 : capture trigger input so20 : serial output ic : internally connected ss20 : chip select input intp0-intp3 : interrupt from peripherals ti80, ti81 : timer input nc : non-connection to80-to82, to90 : timer output p00-p05 : port 0 txd20 : transmit data p10, p11 : port 1 v dd : power supply p20-p26 : port 2 v ss : ground p30-p33 : port 3 x1, x2 : crystal (main system clock) p50-p53 : port 5 xt1, xt2 : crystal (subsystem clock) p60-p67 : port 6
preliminary product information 12 m m m m pd789166y, 789167y, 789176y, 789177y 2. block diagram 78k/0s cpu core rom ram v dd v ss ic ti80/ss20/p25 8-bit timer80 p00-p05 port0 p10, p11 port1 p20-p26 port2 p30-p33 port3 p50-p53 port5 p60-p67 port6 system control 8-bit timer81 8-bit timer82 16-bit timer90 watch timer watchdog timer multiplier sio20 to80/p26 ti81/intp0/cpt90/p30 to81/intp1/p31 cpt90/intp0/ti81/p30 to90/intp2/p32 bzo90/intp3/to82/p33 to82/intp3/bzo90/p33 sck20/asck20/p20 si20/r x d20/p22 so20/t x d20/p21 ss20/ti80/p25 smb0 sda0/p24 ani0/p60- ani7/p67 scl0/p23 av dd av ss av ref a/d converter reset x1 x2 xt1 xt2 interrupt control intp0/ti81/cpt90/p30 intp1/to81/p31 intp2/to90/p32 intp3/to82/bzo90/p33 remark the size of the internal rom varies depending on the model.
preliminary product information 13 m m m m pd789166y, 789167y, 789176y, 789177y 3. pin functions 3.1 port pins pin name i/o function when reset also used as p00-p05 i/o port 0 6-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be set by software. input - p10, p11 i/o port 1 2-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be set by software. input - p20 i/o input sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 scl0 p24 sda0 p25 ti80/ss20 p26 to80 p30 i/o input intp0/ti81/cpt90 p31 intp1/to81 p32 intp2/to90 p33 intp3/to82/bzo90 p50-p53 i/o port 5 4-bit n-channel open-drain input/output port can be set to either input or output in 1-bit units whether to incorporate a pull-up resistor can be set by a mask option. input - p60-p67 input port 6 8-bit input-only port input ani0-ani7 port 2 7-bit input/output port can be set to either input or output in 1-bit units for p20 to p22, p25, and p26, whether to use the on-chip pull-up resistor can be set by software. only p23 and p24 can be used as n-channel open-drain input/output port pins. port 3 4-bit input/output port can be set to either input or output in 1-bit units whether to use the on-chip pull-up resistor can be set by software.
preliminary product information 14 m m m m pd789166y, 789167y, 789176y, 789177y 3.2 non-port pins pin name i/o function when reset also used as intp0 input input p30/ti81/cpt90 intp1 p31/to81 intp2 p32/to90 intp3 p33/to82/bzo90 si20 input serial data input to serial interface input p22/rxd20 so20 output serial data output from serial interface input p21/txd20 sck20 i/o serial clock input/output for serial interface input p20/asck20 asck20 input serial clock input to asynchronous serial interface input p20/sck20 rxd20 input serial data input to asynchronous serial interface input p22/si20 txd20 output serial data output from asynchronous serial interface input p21/so20 scl0 i/o smb0 clock input/output input p23 sda0 i/o smb0 data input/output input p24 ss20 i nput chip select input to serial interface input p25/ti80 ti80 input external count clock input to 8-bit timer (tm80) input p25/ss20 ti81 input external count clock input to 8-bit timer (tm81) input p30/intp0/cpt90 to80 output 8-bit timer (tm80) output input p26 to81 output 8-bit timer (tm81) output input p31/intp1 to82 output 8-bit timer (tm82) output input p33/intp3/bzo90 to90 output 16-bit timer (tm90) output input p32/intp2 cpt90 input capture edge input input p30/intp0/ti81 bzo90 output buzzer output input p33/intp3/to82 ani0-ani7 input a/d converter analog input input p60-p67 av ref - a/d converter reference voltage -- av ss - a/d converter ground potential -- av dd - a/d converter analog power supply -- x1 input connected to crystal for main system clock oscillation -- x2 - -- xt1 input connected to crystal for subsystem clock oscillation -- xt2 - -- reset input system reset input input - v dd - positive supply voltage -- v ss - ground potential -- ic - this pin is internally connected. connect this pin directly to the v ss pin. -- nc - this pin is not connected internally. connect this pin to the v ss pin (or leave this pin open). -- external interrupt input for which effective edges (rising and/or falling edges) can be set
preliminary product information 15 m m m m pd789166y, 789167y, 789176y, 789177y 3.3 pin input/output circuits and handling of unused pins table 3-1 lists the types of input/output circuits for each pin and explains how unused pins are handled. figure 3-1 shows the configuration of each type of input/output circuit. table 3-1. type of input/output circuit for each pin and handling of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00-p05 5-a i/o connect these pins to the v dd or v ss pin via respective resistors. p10, p11 p20/sck20/asck20 8-a p21/so20/txd20 p22/si20/rxd20 p23/scl0 13-aa p24/sda0 p25/ti80/ss20 8-c p26/to80 p30/intp0/ti81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 p50-p53 13-w p60/ani0-p67/ani7 9-c input xt1 - input connect this pin to the v ss pin. xt2 - leave this pin open. reset 2 input - ic -- connect this pin directly to the v ss pin. nc --
preliminary product information 16 m m m m pd789166y, 789167y, 789176y, 789177y figure 3-1. pin input/output circuits schmitt trigger input with hysteresis type 2 in type 5-a pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch type 13-w v ss v ss type 8-a pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch v ss type 9-c in comparator + e v ref (threshold voltage) av ss p-ch n-ch input enable type 13-aa output data output disable in/out v dd n-ch input buffer with intermediate withstand voltage input enable pull-up resistor (mask option) v ss output data output disable in/out input buffer with 5-v withstand voltage comparator n-ch
preliminary product information 17 m m m m pd789166y, 789167y, 789176y, 789177y 4. cpu architecture 4.1 memory space the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y can each access up to 64 kbytes of memory space. figure 4-1 shows the memory map. figure 4-1. memory map special function register 256 8 bits internal high-speed ram 512 8 bits program memory space data memory space program area program area callt table area unusable vector table area internal rom note ffffh ff00h feffh fd00h fcffh nnnnh 0080h 007fh 0040h 003fh 0024h 0023h 0000h 0000h nnnnh nnnnh+1 note the size of the internal rom varies depending on the model (see the following table). product name last address of internal rom nnnnh m pd789166y and m pd789176y 3fffh m pd789167y and m PD789177Y 5fffh
preliminary product information 18 m m m m pd789166y, 789167y, 789176y, 789177y 4.2 data memory addressing each of the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. a data memory area (fd00h to ffffh) can be accessed using a unique addressing mode according to its use, such as a special function register (sfr). figure 4-2 illustrates the data memory addressing modes. figure 4-2. data memory addressing modes special function register (sfr) 256 8 bits internal high-speed ram 512 8 bits internal rom note direct addressing register indirect addressing based addressing sfr addressing short direct addressing unusable ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fd00h fcffh nnnnh 0000h nnnnh+1 note the size of internal rom varies depending on the model (see the following table). product name last address of internal rom nnnnh m pd789166y and m pd789176y 3fffh m pd789167y and m PD789177Y 5fffh
preliminary product information 19 m m m m pd789166y, 789167y, 789176y, 789177y 4.3 processor registers 4.3.1 controller registers (1) program counter (pc) the pc is a 16-bit register for holding address information that indicates the next program to be executed. figure 4-3. program counter configuration pc15 pc pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 15 0 (2) program status word (psw) the psw is an 8-bit register for holding the status of the cpu according to the results of instruction execution. figure 4-4. program status word configuration 7 ie 0 z 0 ac 0 0 1 cy psw (a) interrupt enable flag (ie) ie is used to control whether interrupt requests are to be accepted by the cpu. (b) zero flag (z) z is set (1) if the result of operation is zero. otherwise, it is reset (0). (c) auxiliary carry flag (ac) ac is set (1) if the result of the operation has a carry from bit 3 or a borrow to bit 3. otherwise, it is reset (0). (d) carry flag (cy) cy is used to indicate whether an overflow or underflow has occurred during the execution of a subtract or add instruction. (3) stack pointer (sp) sp is a 16-bit register for holding the start address of a stack area. the stack area can be specified only in an area (fd00h to feffh) of internal high-speed ram. figure 4-5. stack pointer configuration sp15 sp sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 15 0 caution a reset input makes the sp content undefined. before executing an instruction, always initialize the sp.
preliminary product information 20 m m m m pd789166y, 789167y, 789176y, 789177y 4.3.2 general-purpose registers each device has eight 8-bit general-purpose registers (x, a, c, b, e, d, l, and h). these registers can be used as 16-bit registers (two 8-bit registers used in pairs like ax, bc, de, and hl) as well as ordinary 8-bit registers. these registers are identified using functional register names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute register names (r0 to r7 and rp0 to rp3). figure 4-6. general-purpose register configuration (a) absolute register names r7 r6 r5 r4 r3 r2 r1 r0 8-bit processing 16-bit processing rp3 rp2 rp1 rp0 15 0 7 0 (b) functional register names h l d e b c a x 8-bit processing 16-bit processing hl de bc ax 15 0 7 0
preliminary product information 21 m m m m pd789166y, 789167y, 789176y, 789177y 4.3.3 special function registers (sfrs) the sfrs are used as peripheral hardware mode registers and control registers. they are mapped in a 256-byte space, from ff00h to ffffh. table 4-1. special function registers (1/3) address special function register (sfr) name symbol r/w number of bits manipulated simultaneously when reset 1 bit 8 bits 16 bits ff00h port 0 p0 r/w oo- 00h ff01h port 1 p1 oo- ff02h port 2 p2 oo- ff03h port 3 p3 oo- ff05h port 5 p5 oo- ff06h port 6 p6 r oo- ff10h mul0l r - o note 2 o note 3 undefined ff11h mul0h ff14h a/d conversion result register 0 note 4 adcr0 r -oo ff15h ff16h 16-bit compare register 90 cr90l w - o note 2 o note 3 ffffh ff17h cr90h ff18h 16-bit timer register 90 tm90l r - o note 2 o note 3 0000h ff19h tm90h ff1ah 16-bit capture register 90 tcp90l - o note 2 o note 3 undefined ff1bh tcp90h ff20h port mode register 0 pm0 r/w oo- ffh ff21h port mode register 1 pm1 oo- ff22h port mode register 2 pm2 oo- ff23h port mode register 3 pm3 oo- ff25h port mode register 5 pm5 oo- ff32h pull-up resistor option register b2 pub2 oo- 00h ff33h pull-up resistor option register b3 pub3 oo- ff42h timer clock selection register 2 tcl2 oo- notes 1. mul0, cr90, tm90, and tcp90 are those sfr symbols used only in 16-bit access mode. 2. mul0, cr90, tm90, and tcp90 are designed only for 16-bit access. with direct addressing, however, they can also be accessed in 8-bit mode. 3. 16-bit access is allowed only with short direct addressing. 4. when 8-bit a/d converters are used (for the m pd789166y and m pd789167y), this register can be accessed only in 8-bit mode. in this case, the address is assumed to be ff15h. when 10-bit a/d converters are used (for the m pd789176y and m PD789177Y), this register can be accessed only in 16-bit mode. when the m pd78f9177y is used as flash memory for the m pd789166y or m pd789167y, 8-bit access is allowed. however, only those object files generated by an assembler used with the m pd789166y or m pd789167y are supported for this access. 16-bit multiplication result storage register 0 note 1 mul0 note 1 cr90 note 1 tm90 note 1 tcp90
preliminary product information 22 m m m m pd789166y, 789167y, 789176y, 789177y table 4-1. special function registers (2/3) address special function register (sfr) name symbol r/w number of bits manipulated simultaneously when reset 1 bit 8 bits 16 bits ff48h 16-bit timer m ode control register 90 tmc90 r/w oo- 00h ff49h buzzer output control register 90 bzc90 oo- ff4ah clock timer mode control register wtm oo- ff50h 8-bit compare register 80 cr80 w -o- undefined ff51h 8-bit timer register 80 tm80 r -o- 00h ff53h 8-bit timer mode control register 80 tmc80 r/w oo- ff54h 8-bit compare register 81 cr81 w -o- undefined ff55h 8-bit timer register 81 tm81 r -o- 00h ff57h 8-bit timer mode control register 81 tmc81 r/w oo- ff58h 8-bit compare register 82 cr82 w -o- undefined ff59h 8-bit timer register 82 tm82 r -o- 00h ff5bh 8-bit timer mode control register 82 tmc82 r/w oo- ff70h asynchronous serial interface mode register 20 asim20 oo- ff71h asynchronous serial interface status register 20 asis20 r -o- ff72h serial operation mode register 20 csim20 r/w oo- ff73h baud rate generator control register 20 brgc20 oo- ff74h transmission shift register 20 txs20 sio20 w -o- ffh reception buffer register 20 rxb20 r -o- undefined ff78h smb control register 0 smbc0 r/w oo- 00h ff79h smb status register 0 smbs0 r oo- ff7ah smb clock selection register 0 smbcl0 r/w oo- ff7bh smb slave address register 0 smbsva0 oo- ff7ch smb mode register 0 smbm0 oo- 20h ff7dh smb input level setting register 0 smbvi0 oo- 00h ff7eh smb shift register 0 smb0 oo- ff80h a/d converter mode register 0 adm0 oo- ff84h a/d input selection register 0 ads0 oo- ffd0h multiplication data register a0 mra0 w oo- undefined ffd1h multiplication data register b0 mrb0 oo- ffd2h multiplier control register 0 mulc0 r/w oo- 00h ffe0h interrupt request flag register 0 if0 oo- ffe1h interrupt request flag register 1 if1 oo-
preliminary product information 23 m m m m pd789166y, 789167y, 789176y, 789177y table 4-1. special function registers (3/3) address special function register (sfr) name symbol r/w number of bits manipulated simultaneously when reset 1 bit 8 bits 16 bits ffe4h interrupt mask flag register 0 mk0 r/w oo- ffh ffe5h interrupt mask flag register 1 mk1 oo- ffech external interrupt mode register 0 intm0 -o- 00h ffedh external interrupt mode register 1 intm1 -o- fff0h suboscillation mode register sckm oo- fff2h subclock control register css oo- fff7h pull-up resistor option register 0 pu0 oo- fff9h watchdog timer mode register wdtm oo- fffah oscillation settling time selection register osts -o- 04h fffbh processor clock control register pcc oo- 02h
preliminary product information 24 m m m m pd789166y, 789167y, 789176y, 789177y 5. peripheral hardware functions 5.1 ports 5.1.1 port functions the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y are provided with the ports shown in figure 5-1. these ports are used to enable several types of control. table 5-1 lists the functions of each port. these ports, while originally designed as digital input/output ports, can also be used for other functions, as summarized in chapter 3 . figure 5-1. port types p30 p33 p00 p05 port 3 port 0 p50 p53 port 5 p60 p67 port 6 p20 p26 port 2 p10 p11 port 1
preliminary product information 25 m m m m pd789166y, 789167y, 789176y, 789177y table 5-1. port functions port name pin name description port 0 p00-p05 input/output port. each bit of the port can be separately specified as being for input or output. a port used for input can be connected to an on-chip pull-up resistor by means of software specification. port 1 p10, p11 input/output port. each bit of the port can be separately specified as being for input or output. a port used for input can be connected to an on-chip pull-up resistor by means of software specification. port 2 p20-p26 input/output port. each bit of the port can be separately specified as being for input or output. each of p20 to p22, p25, and p26 can be connected to an on-chip pull-up resistor by means of software specification. (p23 and p24 are used as n-channel open-drain input/output ports (with 5-v withstand voltage).) port 3 p30-p33 input/output port. each bit of the port can be separately specified as being for input or output. the port can be connected to an on-chip pull-up resistor by means of software specification. port 5 p50-p53 n-channel open-drain input/output port. each bit of the port can be separately specified as being for input or output. whether the port itself is to contain a pull-up resistor is specified with a mask option. port 6 p60-p67 input-only port
preliminary product information 26 m m m m pd789166y, 789167y, 789176y, 789177y 5.1.2 port configuration the hardware configuration of the ports is as follows. table 5-2. port configuration item configuration control register port mode register (pmm, where m = 0, 1, 2, 3, or 5) pull-up resistor option registers (pu0, pub2, and pub3) port pins total: 31 (17 cmos input/output, 8 cmos input-only, and 6 n-ch open-drain input/output pins) pull-up resistors total: 21 (on-chip pull-up resistors can be used as specified by software, and whether a port itself is to contain pull-up resistors can be specified with a mask option) figure 5-2. basic cmos port configuration internal bus selector wr pum note wr portm wr portm wr pmm output latch (pmn) pmmn v dd p-ch pmn note each bit of the pull-up resistor option registers (pu0, pub2, and pub3) pu00 and pu01 for pu0 pub20 to pub22, pub25, and pub26 for pub2 pub30 to pub33 for pub3 for details, see (2) in section 5.1.3 . caution figure 5-2 shows the basic configuration of the cmos input/output ports. the configuration differs depending on the functions assigned to the dual-function pins. p23, p24, and port 5 are not included in the basic configuration because they are used as n-channel open-drain input/output ports.
preliminary product information 27 m m m m pd789166y, 789167y, 789176y, 789177y remark pmmn : bit n of port mode register m, where m = 0 to 3 and n = 0 to 7 pmn : bit n of port m rd : port read signal wr : port write signal for details, see (2) in section 5.1.3 . 5.1.3 port function control registers the following two types of registers are used to control the ports. ? port mode registers (pm0 to pm3, and pm5) ? pull-up resistor option registers (pu0, pub2, and pub3) (1) port mode registers (pm0 to pm3, and pm5) the port mode registers separately specify each port bit as being for input or output. each port mode register is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input writes ffh into the port mode registers. when port pins are used for secondary functions, the corresponding port mode register and output latch must be set or reset as described in table 5-3. caution when port 3 is acting as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as the input for an external interrupt. to use port 3 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
preliminary product information 28 m m m m pd789166y, 789167y, 789176y, 789177y table 5-3. port mode register and output latch settings for using secondary functions pin name secondary function pm p name input/output p23 scl0 input/output 0 0 p24 sda0 input/output 0 0 p25 ti80 input 1 p26 to80 output 0 0 p30 intp0 input 1 ti81 input 1 cpt90 input 1 p31 intp1 input 1 to81 output 0 0 p32 intp2 input 1 to90 output 0 0 p33 intp3 input 1 to82 output 0 0 bzo90 output 0 0 p60-p67 ani0-ani7 input 1 caution when port 2 is being used as a serial interface, it is necessary to specify whether the port is an input or output port, and to set the output latch accordingly. see table 5-13 for an explanation of how to make this specification. remark : dont care pm : port mode register p : port output latch
preliminary product information 29 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-3. format of port mode register 1 1 pm05 pm04 pm03 pm02 pm01 pm00 pm0 symbol address when reset r/w ff20h ffh r/w ffh r/w ffh r/w ffh r/w ffh r/w 6 7 0 5432 1 1 1 1 1 1 1 pm11 pm10 pm1 ff21h 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 ff22h 1 1 1 1 pm33 pm32 pm31 pm30 pm3 ff23h 1 1 1 1 pm53 pm52 pm51 pm50 pm5 ff25h pmmn pmn pin input/output mode selection (m = 0 to 3 or 5; n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 0 1 (2) pull-up resistor option registers (pu0, pub2, pub3) these registers are used to specify pull-up resistor connection on a port-by-port basis and bit-by-bit basis. the method of pull-up resistor connection varies, depending on whether a connection is made on a port-by- port basis or bit-by-bit basis as described below. (a) pull-up resistor option register (pu0) this register is used for port-by-port specification. an on-chip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the on-chip pull-up resistor is specified using pu0. for those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of pu0. this also applies to a dual-function pin used as an output pin. a reset input clears pu0 to 00h. (b) pull-up resistor option registers (pub2, pub3) these registers are used for bit-by-bit specification. by setting pub2 or pub3, an on-chip pull-up resistor can be used, regardless of the setting of the port mode register. a reset input clears pub2 and pub3 to 00h.
preliminary product information 30 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-4. format of pull-up resistor option register 0 pu0m pm on-chip pull-up resistor selection (m = 0 or 1) on-chip pull-up resistor not used on-chip pull-up resistor used 0 1 0 0 0 0 0 0 pu01 pu00 pu0 symbol address when reset r/w fff7h 00h r/w 6 7543 2 note 1 0 note for each port, pu0 selects whether on-chip pull-up resistors are to be used. caution bits 2 to 7 must be fixed to 0. figure 5-5. format of pull-up resistor option register b2 pub2m p2m on-chip pull-up resistor selection (m = 0 to 2, 5, or 6) on-chip pull-up resistor not used on-chip pull-up resistor used 0 1 0 pub26 pub25 0 0 pub22 pub21 pub20 pub2 symbol address when reset r/w ff32h 00h r/w 743 note 6 5 2 1 0 note pub2 selects whether on-chip pull-up resistors are to be used in 1-bit units. caution bits 3, 4, and 7 must be fixed to 0. figure 5-6. format of pull-up resistor option register b3 pub3m p3m on-chip pull-up resistor selection (m = 0 to 3) on-chip pull-up resistor not used on-chip pull-up resistor used 0 1 0 0 0 0 pub33 pub32 pub31 pub30 pub3 symbol address when reset r/w ff33h 00h r/w 6 754 note 3 21 0 note pub3 selects whether on-chip pull-up resistors are to be used in 1-bit units. caution bits 4 to 7 must be fixed to 0.
preliminary product information 31 m m m m pd789166y, 789167y, 789176y, 789177y 5.2 clock generator 5.2.1 clock generator functions the clock generator generates the clock pulse to be supplied to the cpu and peripheral hardware. there are two types of system clock oscillators: ? main system clock oscillator (ceramic or crystal oscillation) this circuit generates a frequency of 1.0 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or by using the processor clock control register. ? subsystem clock oscillator this circuit generates 32.768 khz. oscillation can be stopped by using the suboscillation mode register. 5.2.2 clock generator configuration the clock generator consists of the following hardware. table 5-4. clock generator configuration item configuration control register processor clock control register (pcc) suboscillation mode register (sckm) subclock control register (css) oscillator main system clock oscillator subsystem clock oscillator
preliminary product information 32 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-7. block diagram of clock generator subsystem clock oscillator main system clock oscillator standby controller wait controller f xt x1 x2 xt1 xt2 f x f x 2 2 f xt 2 1/2 prescaler prescaler 16-bit timer 90 8-bit timer 82 clock timer clock for peripheral hardware cpu clock (f cpu ) selector stop mcc pcc1 cls css0 internal bus suboscillation mode register (sckm) frc scc internal bus subclock control register (css) processor clock control register (pcc)
preliminary product information 33 m m m m pd789166y, 789167y, 789176y, 789177y 5.2.3 clock generator control registers the clock generator is controlled using the following registers. processor clock control register (pcc) suboscillation mode register (sckm) subclock control register (css) (1) processor clock control register (pcc) the pcc selects a cpu clock and specifies a corresponding frequency division ratio. it is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input loads 02h into the pcc. figure 5-8. format of processor clock control register control of main system clock oscillator operation mcc 0 0 0 0 0 pcc1 0 pcc symbol address when reset r/w fffbh 02h r/w 7 6543210 mcc 0 1 operation enabled operation disabled cpu clock (f cpu ) selection note css0 0 0 1 1 f x f x /2 2 f xt /2 pcc1 0 1 0 1 (0.2 s) (0.8 s) (61 s) m m m note a cpu clock is selected by a combination of the pcc1 flag in the processor clock control register (pcc) and the css0 flag in the subclock control register (css). (see (3) in section 5.2.3 .) cautions 1. bit 0 and bits 2 to 6 must be fixed to 0. 2. mcc can be set only when the subsystem clock is selected as the cpu clock. 3. never set mcc when an external clock is applied. this is because the x2 pin is pulled up to v dd . remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. 4. minimum instruction execution time: 2 f cpu f cpu = 0.2 m s : 0.4 m s f cpu = 0.8 m s : 1.6 m s f cpu = 61 m s : 122 m s
preliminary product information 34 m m m m pd789166y, 789167y, 789176y, 789177y (2) suboscillation mode register (sckm) the sckm selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. it is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears sckm to 00h. figure 5-9. format of suboscillation mode register feedback resistor selection 0 0 0 0 0 0 frc scc sckm symbol address when reset r/w fff0h 00h r/w 76543 210 frc 0 1 internal feedback resistor used internal feedback resistor not used control of subsystem clock oscillator operation scc 0 1 operation enabled operation disabled caution bits 2 to 7 must be fixed to 0.
preliminary product information 35 m m m m pd789166y, 789167y, 789176y, 789177y (3) subclock control register (css) the css specifies whether the main system or subsystem clock oscillator is to be selected. it also specifies how the cpu clock operates. it is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears css to 00h. figure 5-10. format of subclock control register cpu clock operation status 0 0 cls css0 0 0 0 0 css address when reset r/w fff2h 00h r/w note 76543210 cls 0 1 operation based on the output of the divided main system clock operation based on the subsystem clock selection of the main system or subsystem clock oscillator css0 0 1 divided output from the main system clock oscillator output form the subsystem clock oscillator symbol note bit 5 is read-only. caution bits 0 to 3, 6, and 7 must be fixed to 0.
preliminary product information 36 m m m m pd789166y, 789167y, 789176y, 789177y 5.3 16-bit timer counter 5.3.1 16-bit timer counter functions 16-bit timer counter 90 (tm90) has the following functions. (1) timer interrupt an interrupt is generated if the tm90 count matches a comparison value. (2) timer output the timer output can be controlled if the count matches a comparison value. (3) count capture the count in tm90 is captured into the capture register in synchronization with a capture trigger. (4) buzzer output the buzzer output can be controlled if the count matches the comparison value. 5.3.2 16-bit timer counter configuration 16-bit timer counter 90 (tm90) consists of the following hardware. table 5-5. 16-bit timer counter 90 configuration item configuration timer register 16 bits 1 (tm90) register compare register 90 : 16 bits 1 (cr90) capture register 90 : 16 bits 1 (tcp90) timer output 1 (to90) control register 16-bit timer mode control register 90 (tmc90) buzzer output control register 90 (bzc90) port mode register 2 (pm2)
preliminary product information 37 m m m m pd789166y, 789167y, 789176y, 789177y internal bus internal bus 16-bit timer mode control register 90 (tmc90) tof90 cpt900 cpt901 edge detection circuit note see figure 5-17 . 16-bit capture register (tcp90) 16-bit counter read buffer 16-bit timer register (tm90) 16-bit compare register (cr90) f x /2 2 f x /2 6 f x /2 7 f xt ctp90/intp0/ ti81/p30 selector selector toc90 tcl901 tcl900 toe90 flip- flop tod90 p32 output latch p33 output latch pm32 pm33 to90/intp2/ p32 inttm90 bzo90/intp3/ to82/p33 to82 output note match ovf buzzer output control register (bzc90) 3 bcs902 bcs901 bcs900 bzoe90 figure 5-11. block diagram of 16-bit timer counter 90
preliminary product information 38 m m m m pd789166y, 789167y, 789176y, 789177y (1) 16-bit compare register 90 (cr90) a value specified in cr90 is compared with the count in 16-bit timer register 90 (tm90). if they match, an interrupt request (inttm90) is issued. cr90 is manipulated using an 8-bit or 16-bit memory manipulation instruction. any value from 0000h to ffffh can be set. a reset input loads ffffh into cr90. cautions 1. cr90 is designed to be manipulated using a 16-bit memory manipulation instruction. it can also be manipulated using 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is used to set cr90, it must be in a direct addressing access mode. 2. to re-set cr90 during count operation, it is necessary to disable interrupts in advance, using an interrupt mask flag register 1 (mk1). it is also necessary to disable inversion of the timer output data, using 16-bit timer mode control register 90 (tmc90). (2) 16-bit timer register 90 (tm90) tm90 is used to count the number of pulses. the contents of tm90 are read using an 8-bit or 16-bit memory manipulation instruction. a reset input clears tm90 to 0000h. cautions 1. the count becomes undefined when stop mode is deselected, because the count operation is performed before oscillation settles. 2. tm90 is designed to be manipulated using a 16-bit memory manipulation instruction. it can also be manipulated using 8-bit memory manipulation instructions, however. when an 8-bit memory instruction is used to manipulate tm90, it must be in a direct addressing access mode. 3. when an 8-bit memory manipulation instruction is used to manipulate tm90, the lower and upper bytes must be read as a pair, in this order. (3) 16-bit capture register 90 (tcp90) tcp90 captures the contents of 16-bit timer 90 (tm90). it is manipulated using an 8-bit or 16-bit memory manipulation instruction. a reset input makes tcp90 undefined. caution tcp90 is designed to be manipulated using a 16-bit memory manipulation instruction. it can also be manipulated using 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is used to manipulate tcp90, it must be in a direct addressing access mode. (4) 16-bit counter read buffer 90 this buffer is used to latch and hold the count for 16-bit timer 90 (tm90).
preliminary product information 39 m m m m pd789166y, 789167y, 789176y, 789177y 5.3.3 16-bit timer counter control registers the following three types of registers are used to control 16-bit timer counter 90 (tm90). ? 16-bit timer mode control register 90 (tmc90) ? buzzer output control register 90 (bzc90) ? port mode register 2 (pm2) (1) 16-bit timer mode control register 90 (tmc90) tmc90 controls the count clock and capture edge settings. it is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears tmc90 to 00h.
preliminary product information 40 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-12. format of 16-bit timer mode control register 90 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 symbol address when reset r/w ff48h 00h r/w note 5 6 43210 7 tof90 0 1 overflow flag control reset or cleared by software set when the 16-bit timer overflows cpt901 0 0 1 1 capture edge selection cpt900 0 1 0 1 capture operation disabled captured at the rising edge at the cpt90 pin captured at the falling edge at the cpt90 pin captured at both the rising and falling edges at the cpt90 pin toc90 0 1 timer output data inversion control inversion disabled inversion enabled tcl901 0 0 1 1 16-bit timer counter 90 count clock selection tcl900 0 1 0 1 toe90 0 1 16-bit timer counter 90 output control output disabled (port mode) output enabled tod90 0 1 timer output data timer output of 0 timer output of 1 f x /2 2 (1.25 mhz) f x /2 6 (78.125 khz) f x /2 7 (39.063 khz) f xt (32.768 khz) note bit 7 is read-only. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
preliminary product information 41 m m m m pd789166y, 789167y, 789176y, 789177y (2) buzzer output control register (bzc90) based on the count clock (fcl) selected with the count clock selection bits (tcl901 and tcl900), this register sets a buzzer frequency and controls square wave output. bzc90 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears bzc90 to 00h. figure 5-13. format of buzzer output control register bzoe90 buzzer port output control disables buzzer port output. enables buzzer port output. note 0 1 0 0 0 0 bcs902 bcs901 bcs900 bzoe90 bzc90 symbol address when reset r/w ff49h 00h r/w 6 754 bcs902 bcs901 bcs900 buzzer frequency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 21 0 fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 7 fcl = f xt fcl/2 4 (78.125 khz) fcl/2 5 (39.063 khz) fcl/2 8 (4,883 hz) fcl/2 9 (2,441 hz) fcl/2 10 (1,221 hz) fcl/2 11 (610 hz) fcl/2 12 (305 hz) fcl/2 13 (153 hz) fcl/2 4 (4,883 hz) fcl/2 5 (2,441 hz) fcl/2 8 (305 hz) fcl/2 9 (153 hz) fcl/2 10 (76 hz) fcl/2 11 (38 hz) fcl/2 12 (19 hz) fcl/2 13 (10 hz) fcl/2 4 (2,441 hz) fcl/2 5 (1,221 hz) fcl/2 8 (153 hz) fcl/2 9 (76 hz) fcl/2 10 (38 hz) fcl/2 11 (19 hz) fcl/2 12 (10 hz) fcl/2 13 (5 hz) fcl/2 4 (2,048 hz) fcl/2 5 (1,024 hz) fcl/2 8 (128 hz) fcl/2 9 (64 hz) fcl/2 10 (32 hz) fcl/2 11 (16 hz) fcl/2 12 (8 hz) fcl/2 13 (4 hz) note when setting bzoe90 to 1, toe82 must be fixed to 0. (see figure 5-20 .) cautions 1. bits 4 to 7 must be fixed to 0. 2. if the subclock is selected as the count clock (tcl901 = 1, tcl900 = 1: see figure 5-12), the subclock is not synchronized when buzzer port output is enabled. in this case, the capture function and tm90 register read function are disabled. in addition, the count value of the tm90 register is undefined. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
preliminary product information 42 m m m m pd789166y, 789167y, 789176y, 789177y (3) port mode register 3 (pm3) pm3 is used to specify port 3 input/output on a bit-by-bit basis. when the p32/intp2/to90 pin is used for timer output, set 0 in the output latch of pm32 and p32. when the p33/intp3/to82/bzo90 pin is used for buzzer output note , set 0 in the output latch of the pm33 and p33. pm3 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input loads ffh into pm3. note never output the to82 and bzo90 signals at the same time. figure 5-14. format of port mode register 3 pm3n p3n pin i/o mode (n = 2 or 3) output mode (output buffer on) input mode (output buffer off) 0 1 1 1 1 1 pm33 pm32 pm31 pm30 pm3 symbol address when reset r/w ff23h ffh r/w 6 754 3 21 0
preliminary product information 43 m m m m pd789166y, 789167y, 789176y, 789177y 5.4 8-bit timer/event counter 5.4.1 8-bit timer/event counter functions devices of the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y have two timer/event counters (tm80 and tm81) and one timer counter (tm82). readers who are seeking a description of tm82 should read the term timer/event counter as timer counter. the 8-bit timer/event counters (tm80, tm81, and tm82) have the following functions. (1) 8-bit interval timer (tm80, tm81, and tm82) this timer causes interrupts to be issued at specified intervals. (2) external event counter (tm80 and tm81) this counter is used to count the number of pulses input from an external source. (3) square wave output (tm80, tm81, and tm82) a square wave of any frequency can be output. (4) pwm output (tm80, tm81, and tm82) pwm output with an 8-bit resolution is supported. table 5-6. 8-bit timer/event counter types and functions tm80 tm81 tm82 type interval timer one channel one channel one channel external event counter oo function timer output ooo square wave output ooo pwm output ooo interrupt request ooo 5.4.2 8-bit timer/event counter configuration the 8-bit timer/event counter consists of the following hardware. table 5-7. 8-bit timer/event counter configuration item configuration timer register 8 bits 3 (tm80, tm81, tm82) register compare registers: 8 bits 3 (cr80, cr81, cr82) timer output 3 (to80, to81, to82) control register 8-bit timer mode control registers 80, 81, 82 (tmc80, tmc81, tmc82) port mode registers 2, 3 (pm2, pm3)
preliminary product information 44 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-15. block diagram of 8-bit timer/event counter 80 internal bus internal bus 8-bit compare register 80 (cr80) 8-bit timer counter 80 (tm80) match clear ovf r s inv q q tce80 pwme80 tcl801 tcl800 toe80 ti80/p25/ ss20 f x f x /2 3 8-bit timer mode control register 80 (tmc80) p26 output latch to80/p26 pm26 inttm80 selector figure 5-16. block diagram of 8-bit timer/event counter 81 internal bus internal bus 8-bit compare register 81 (cr81) 8-bit timer counter 81 (tm81) match clear ovf r s inv q q tce81 pwme81 tcl811 tcl810 toe81 ti81/cpt90/ p30/intp0 f x /2 8 f x /2 4 8-bit timer mode control register 81 (tmc81) p31 output latch to81/p31/ intp1 pm31 inttm81 selector
preliminary product information 45 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-17. block diagram of 8-bit timer counter 82 internal bus internal bus 8-bit compare register 82 (cr82) 8-bit timer counter 82 (tm82) match clear ovf r s inv q q tce82 pwme82 tcl821 tcl820 toe82 f xt f x /2 7 f x /2 5 8-bit timer mode control register 82 (tmc82) p33 output latch to82/bzo90/ p33/intp3 pm33 inttm82 bzo90 output note selector note see figure 5-11 . (1) 8-bit compare register 8n (cr8n) a value specified in cr8n is compared with the count in 8-bit timer register 8n (tm8n). if they match, an interrupt request (inttm8n) is issued. cr8n is manipulated using an 8-bit memory manipulation instruction. any value from 00h to ffh can be set. a reset input makes cr8n undefined. remark n = 0 to 2 (2) 8-bit timer register 8n (tm8n) tm8n is used to count the number of pulses. its contents are read using an 8-bit memory manipulation instruction. a reset input clears tm8n to 00h. remark n = 0 to 2
preliminary product information 46 m m m m pd789166y, 789167y, 789176y, 789177y 5.4.3 8-bit timer/event counter control registers the following two types of registers are used to control the 8-bit timer/event counter. ? 8-bit timer mode control registers 80, 81, and 82 (tmc80, tmc81, and tmc82) ? port mode registers 2 and 3 (pm2 and pm3) (1) 8-bit timer mode control register 80 (tmc80) tmc80 determines whether to enable or disable 8-bit timer register 80 (tm80) and specifies the count clock for tm80. it also controls the operation of the output control circuit of 8-bit timer counter 80. tmc80 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears tmc80 to 00h. figure 5-18. format of 8-bit timer mode control register 80 tce80 pwme80 000 tcl801tcl800 toe80 tmc80 symbol address when reset r/w ff53h 00h r/w 6 7 543210 tcl801 0 0 1 1 8-bit timer register 80 count clock selection tcl800 0 1 0 1 f x f x /2 3 rising edge of ti80 falling edge of ti80 tce80 0 1 8-bit timer register 80 operation control operation disabled (tm80 is cleared to 0.) operation enabled pwme80 0 1 pwm output selection counter operation pwm output (5.0 mhz) (625 khz) toe80 0 1 8-bit timer counter 80 output control output disabled (port mode) output enabled cautions 1. always stop the timer before setting tmc80. 2. for pwm mode operation, the interrupt mask flag (tmmk80) must be set. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
preliminary product information 47 m m m m pd789166y, 789167y, 789176y, 789177y (2) 8-bit timer mode control register 81 (tmc81) tmc81 determines whether to enable or disable 8-bit timer register 81 (tm81) and specifies the count clock for tm81. it also controls the operation of the output control circuit of 8-bit timer counter 81. tmc81 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears tmc81 to 00h. figure 5-19. format of 8-bit timer mode control register 81 tce81 pwme81 000 tcl811tcl810 toe81 tmc81 symbol address when reset r/w ff57h 00h r/w 6 7 543210 tcl811 0 0 1 1 8-bit timer register 81 count clock selection tcl810 0 1 0 1 f x /2 4 f x /2 8 rising edge of ti81 falling edge of ti81 tce81 0 1 8-bit timer register 81 operation control operation disabled (tm81 is cleared to 0.) operation enabled pwme81 0 1 pwm output selection counter operation pwm output (312.5 khz) (19.5 khz) toe81 0 1 8-bit timer counter 81 output control output disabled (port mode) output enabled cautions 1. always stop the timer before setting tmc81. 2. for pwm mode operation, the interrupt mask flag (tmmk81) must be set. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
preliminary product information 48 m m m m pd789166y, 789167y, 789176y, 789177y (3) 8-bit timer mode control register 82 (tmc82) tmc82 determines whether to enable or disable 8-bit timer register 82 (tm82) and specifies the count clock for tm82. it also controls the operation of the output control circuit of 8-bit timer counter 82. tmc82 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears tmc82 to 00h. figure 5-20. format of 8-bit timer mode control register 82 tce82 pwme82 000 tcl821tcl820 toe82 tmc82 symbol address when reset r/w ff5bh 00h r/w 6 7 543210 tcl821 0 0 1 1 8-bit timer register 82 count clock selection tcl820 0 1 0 1 f x /2 5 f x /2 7 f xt not to be set tce82 0 1 8-bit timer register 82 operation control operation disabled (tm82 is cleared to 0.) operation enabled pwme82 0 1 pwm output selection counter operation pwm output (156.25 khz) (39.1 khz) (32.768 khz) toe82 0 1 8-bit timer counter 82 output control output disabled (port mode) output enabled note note when toe82 is set to 1, bzoe90 must be set to 0 (see figure 5-13 ). cautions 1. always stop the timer before setting tmc82. 2. for pwm mode operation, the interrupt mask flag (tmmk82) must be set. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
preliminary product information 49 m m m m pd789166y, 789167y, 789176y, 789177y (4) port mode registers 2 and 3 (pm2 and pm3) pm2 and pm3 specify whether each bit of port 2 and port 3 is used for input or output. to use the p26/to80 pin for timer output, the pm26 and p26 output latches must be reset to 0. to use the p31/to81/intp1 pin for timer output, the pm31 and p31 output latches must be reset to 0. to use the p33/intp3/to82/bzo90 pin for timer output, the pm33 and p33 output latches must be reset to 0. pm2 and pm3 are manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input loads ffh into pm2 and pm3. figure 5-21. format of port mode register 2 pm26 0 1 p26 pin input/output mode selection output mode (output buffer on) input mode (output buffer off) 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 7654 symbol address when reset r/w ff22h ffh r/w 32 10 figure 5-22. format of port mode register 3 pm31 0 1 p31 pin input/output mode selection output mode (output buffer on) input mode (output buffer off) 1 1 1 1 pm33 pm32 pm31 pm30 pm3 76 54 symbol address when reset r/w ff23h ffh r/w pm33 0 1 p33 pin input/output mode selection output mode (output buffer on) input mode (output buffer off) 3210
preliminary product information 50 m m m m pd789166y, 789167y, 789176y, 789177y 5.5 clock timer 5.5.1 clock timer functions the clock timer has the following functions. ? clock timer ? interval timer the clock and interval timers can be used at the same time. figure 5-23 is a block diagram of the clock timer. figure 5-23. block diagram of clock timer f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selector clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 clock timer mode control register (wtm) internal bus selector
preliminary product information 51 m m m m pd789166y, 789167y, 789176y, 789177y (1) clock timer the 4.19-mhz main system clock or 32.768-khz subsystem clock is used to issue an interrupt request (intwt) at 0.5-second intervals. caution when the main system clock is operating at 5.0 mhz, it cannot be used to generate a 0.5-second interval. in this case, the subsystem clock, which operates at 32.768 khz, should be used instead. (2) interval timer the interval timer is used to generate an interrupt request (intwti) at specified intervals. table 5-8. interval generated using the interval timer interval operation at f x = 5.0 mhz operation at f x = 4.19 mhz operation at f xt = 32.768 khz 2 4 1/f w 409.6 m s 489 m s 488 m s 2 5 1/f w 819.2 m s 978 m s 977 m s 2 6 1/f w 1.64 ms 1.96 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.82 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remark f w : clock timer clock frequency (f x /2 7 or f xt ) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 5.5.2 clock timer configuration the clock timer consists of the following hardware. table 5-9. clock timer configuration item configuration counter 5 bits prescaler 9 bits control register clock timer mode control register (wtm)
preliminary product information 52 m m m m pd789166y, 789167y, 789176y, 789177y 5.5.3 clock timer control register the clock timer mode control register (wtm) is used to control the clock timer. ? clock timer mode control register (wtm) the wtm selects a count clock for the clock timer and specifies whether to enable clocking of the timer. it also specifies the prescaler interval and how the 5-bit counter is controlled. the wtm is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears the wtm to 00h. figure 5-24. format of clock timer mode control register clock timer count clock selection wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm symbol address when reset r/w ff4ah 00h r/w 76543210 wtm7 0 1 prescaler interval selection wtm6 0 0 0 0 1 1 2 4 /f w 2 5 /f w 2 6 /f w 2 7 /f w 2 8 /f w 2 9 /f w wtm5 0 0 1 1 0 0 wtm4 0 1 0 1 0 1 5-bit counter operation control wtm1 0 1 cleared after stop started clock timer operation wtm0 0 1 operation disabled (both prescaler and timer cleared) operation enabled other settings f x /2 7 f xt (39.1 khz) (32.768 khz) not to be set remarks 1. f w : clock timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
preliminary product information 53 m m m m pd789166y, 789167y, 789176y, 789177y 5.6 watchdog timer 5.6.1 watchdog timer functions the watchdog timer has the following functions. (1) watchdog timer the watchdog timer is used to detect unintended program loops. if an unintended program loop is detected, a nonmaskable interrupt or reset signal is generated. (2) interval timer the interval timer is used to generate interrupts at specified intervals. 5.6.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 5-10. watchdog timer configuration item configuration control register timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm)
preliminary product information 54 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-25. block diagram of watchdog timer internal bus internal bus prescaler f x 2 6 f x 2 8 f x 2 10 3 7-bit counter run clear tmif4 tmmk4 tcl22 tcl21 tcl20 timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) wdtm4 wdtm3 intwdt maskable interrupt request reset intwdt nonmaskable interrupt request f x 2 4 selector control circuit
preliminary product information 55 m m m m pd789166y, 789167y, 789176y, 789177y 5.6.3 watchdog timer control registers the following two types of registers are used to control the watchdog timer. ? timer clock selection register 2 (tcl2) ? watchdog timer mode register (wdtm) (1) timer clock selection register 2 (tcl2) tcl2 specifies the count clock for the watchdog timer. tcl2 is manipulated using an 8-bit memory manipulation instruction. a reset input clears tcl2 to 00h. figure 5-26. format of timer clock selection register 2 tcl22 0 0 1 1 watchdog timer count clock selection interval time 00000 tcl22 tcl21 tcl20 tcl2 symbol address when reset r/w ff42h 00h r/w 76543210 tcl21 0 1 0 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 not to be set (312.5 khz) (78.1 khz) (19.5 khz) (4.88 khz) (410 s) (1.64 ms) (6.55 ms) (26.2 ms) m other settings tcl20 0 0 0 0 2 11 /f x 2 13 /f x 2 15 /f x 2 17 /f x remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
preliminary product information 56 m m m m pd789166y, 789167y, 789176y, 789177y (2) watchdog timer mode register (wdtm) the wdtm specifies the watchdog timer operation mode and whether to enable or disable counting. the wdtm is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears the wdtm to 00h. figure 5-27. format of watchdog timer mode register run 0 1 watchdog timer operation selection note 1 run 0 0 wdtm4 wdtm3 000 wdtm symbol address when reset r/w fff9h 00h r/w 6 7 543210 stops counting. clears the counter and causes it to start. wdtm4 0 0 1 1 watchdog timer operation mode selection note 2 wdtm3 0 1 0 1 operation disabled internal timer mode (when an overflow occurs, a maskable interrupt is issued.) note 3 watchdog timer mode 1 (when an overflow occurs, a nonmaskable interrupt is issued.) watchdog timer mode 2 (when an overflow occurs, a reset operation is started.) notes 1. once the run bit has been set (1), it is impossible to zero-clear it by software. so, once counting begins, it cannot be stopped by any means other than a reset input. 2. once wdtm3 and wdtm4 have been set (1), it is impossible to zero-clear them by software. 3. the interval timer starts operating when the run bit is set to 1. cautions 1. if the run bit is set to 1, and the watchdog timer is cleared, the actual overflow time becomes 0.8% (maximum) less than the time specified in timer clock selection register 2. 2. to use watchdog timer mode 1 or 2, ensure that the interrupt request flag (tmif4) is set to 0, before setting wdtm4 to 1. if tmif4 is set to 1, selecting mode 1 or 2 causes a nonmaskable interrupt to be issued at the instant rewriting ends.
preliminary product information 57 m m m m pd789166y, 789167y, 789176y, 789177y 5.7 a/d converter a/d converters support different conversion resolutions, depending on the microcontroller model, as shown below: a/d converters with an 8-bit resolution: for m pd789166y and m pd789167y a/d converters with a 10-bit resolution: for m pd789176y and m PD789177Y 5.7.1 a/d converter functions the a/d converter converts input analog voltages to digital signals with an 8-bit or 10-bit resolution. it can control up to eight analog input channels (ani0 to ani7). a/d conversion can be started only by software. one of analog inputs ani0 to ani7 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued each time an a/d conversion is completed. caution in standby mode, the a/d converter operation is disabled. 5.7.2 a/d converter configuration the a/d converter consists of the following hardware. table 5-11. a/d converter configuration item configuration analog input 8 channels (ani0 to ani7) register successive approximation register (sar) a/d conversion result register 0 (adcr0) control register a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0)
preliminary product information 58 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-28. block diagram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 sample-and-hold circuit voltage comparator control circuit successive approximation register (sar) 3 a/d conversion result register 0 (adcr0) tap selector selector av ss intad a/d conveter mode register 0 (adm0) a/d input selection register 0 (ads0) internal bus av ss adcs0 0 fr02 fr01 fr00 0 0 0 ads02ads01ads00 av ref av dd ani7 (1) successive approximation register (sar) the sar receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the serial resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least significant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to the a/d conversion result register. (2) a/d conversion result register 0 (adcr0) the adcr holds the result of a/d conversion. each time a/d conversion ends, the conversion result received from the successive approximation register is loaded into the adcr0. for the m pd789166y and m pd789167y (featuring 8-bit a/d converters), the value of adcr0 is read using an 8-bit memory manipulation instruction. for the m pd789176y and m PD789177Y (featuring 10-bit a/d converters), the value of adcr0 is read using a 16-bit memory manipulation instruction. a reset input makes adcr0 undefined. caution when 8-bit a/d converters are used (for the m m m m pd789166y and m m m m pd789167y), this register can be accessed only in 8-bit mode. in this case, the address is assumed to be ff15h. when 10-bit a/d converters are used (for the m m m m pd789176y and m m m m PD789177Y), this register can be accessed only in 16-bit mode. when the m m m m pd78f9177y is used as flash memory for the m m m m pd789166y or m m m m pd789167y, 8-bit access is allowed. however, only those object files generated by an assembler used with the m m m m pd789166y or m m m m pd789167y are supported for this access.
preliminary product information 59 m m m m pd789166y, 789167y, 789176y, 789177y (3) sample-and-hold circuit the sample-and-hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion. (4) voltage comparator the voltage comparator compares an analog input with the voltage output by the serial resistor string. (5) serial resistor string the serial resistor string is configured between av ref and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani7 pins pins ani0 to ani7 are 8-channel analog input pins for the a/d converter. they are used to receive the analog signals to be subject to a/d conversion. caution do not supply pins ani0 to ani7 with voltages that fall outside the rated range. if a voltage greater than av ref or less than av ss (even if within the absolute maximum rating) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. furthermore, the conversion values for the other channels may also be affected. (7) av ref pin the av ref pin is a reference voltage pin for the a/d converter. signals received at pins ani0 to ani7 are converted to digital signals while referencing the voltage across the av ref and av ss pins. (8) av ss pin the av ss pin is a ground potential pin for the a/d converter. this pin must be held at the same potential as the v ss pin, even while the a/d converter is not being used. (9) av dd pin the av dd pin is an analog power supply pin for the a/d converter. this pin must be held at the same potential as the v dd pin, even while the a/d converter is not being used.
preliminary product information 60 m m m m pd789166y, 789167y, 789176y, 789177y 5.7.3 a/d converter control registers the following two types of registers are used to control the a/d converter. ? a/d converter mode register 0 (adm0) ? a/d input selection register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears adm0 to 00h. figure 5-29. format of a/d converter mode register 0 a/d conversion control adcs0 0 fr02 fr01 fr00 0 0 0 adm0 symbol address when reset r/w ff80h 00h r/w 76543210 adcs0 0 1 a/d conversion time selection note 1 fr02 0 0 0 1 1 1 144/fx 120/fx 96/fx 72/fx 60/fx 48/fx fr01 0 0 1 0 0 1 (28.8 s) (24 s) (19.2 s) (14.4 s) (not to be set note 2 ) (not to be set note 2 ) m m m fr00 0 1 0 0 1 0 other settings conversion disabled conversion enabled not to be set m notes 1. the specifications of fr02, fr01, and fr00 must be such that the a/d conversion time is at least 14 m s. 2. these bit combinations must not be used, as the a/d conversion time will fall below 14 m s. cautions 1. the result of conversion performed immediately after bit 7 (adcs0) is set is undefined. 2. bits 0 to 2 and bit 6 must be fixed to 0. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
preliminary product information 61 m m m m pd789166y, 789167y, 789176y, 789177y (2) a/d input selection register 0 (ads0) ads0 specifies the port used to input the analog voltages to be converted to a digital signal. the ads0 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears ads0 to 00h. figure 5-30. format of a/d input selection register 0 00000 ads02 ads01 ads00 ads0 symbol address when reset r/w ff84h 00h r/w 76543210 analog input channel specification ads02 0 0 0 0 1 1 1 1 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads01 0 0 1 1 0 0 1 1 ads00 0 1 0 1 0 1 0 1 caution bits 3 to 7 must be fixed to 0.
preliminary product information 62 m m m m pd789166y, 789167y, 789176y, 789177y 5.8 serial interface 5.8.1 serial interface 20 (1) serial interface 20 functions serial interface 20 has the following three types of modes. ? operation stopped mode ? asynchronous serial interface (uart) mode ? three-wire serial i/o mode (a) operation stopped mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (b) asynchronous serial interface (uart) mode this mode is used to send and receive the one byte of data that follows a start bit. it supports full-duplex communication. serial interface 20 contains a dedicated uart baud rate generator, enabling communication over a wide range of baud rates. it is also possible to define baud rates by dividing the frequency of the input clock pulse at the asck20 pin. (c) three-wire serial i/o mode (switchable between msb-first and lsb-first transmission) this mode is used to transmit 8-bit data, using three lines: a serial clock (sck20) line and two serial data lines (si20 and so20). as it supports simultaneous transmission and reception, three-wire serial i/o mode requires less processing time for data transmission than asynchronous serial interface mode. because, in three-wire serial i/o mode, it is possible to select whether 8-bit data transmission begins with the msb or lsb, serial interface 20 can be connected to any device regardless of whether that device is designed for msb-first or lsb-first transmission. three-wire serial i/o mode is useful for connecting peripheral i/o circuits and display controllers having conventional clock synchronous serial interfaces, such as those of the 75x/xl, 78k, and 17k series devices. (2) serial interface 20 configuration serial interface 20 consists of the following hardware. table 5-12. serial interface 20 configuration item configuration register transmission shift register 20 (txs20) reception shift register 20 (rxs20) reception buffer register 20 (rxb20) control register serial operation mode register 20 (csim20) asynchronous serial interface mode register 20 (asim20) asynchronous serial interface status register 20 (asis20) baud rate generator control register 20 (brgc20)
preliminary product information 63 m m m m pd789166y, 789167y, 789176y, 789177y internal bus reception buffer register 20 (rxb20) switching of the first bit asynchronous serial interface status register 20 (asis20) serial operation mode register 20 (csim20) reception shift register 20 (rxs20) csie20 sse20 dap20 dir20 csck20 ckp20 pe20 fe20 ove20 txe20 rxe20 ps201 ps200 cl20 sl20 asynchronous serial interface mode register 20 (asim20) transmission shift register 20 (txs20) transmission shift clock selector csie20 dap20 data phase control reception shift clock si20/p22/ rxd20 so20/p21/ txd20 4 parity operation stop bit addition reception data counter parity operation stop bit addition transmission data counter sl20, cl20, ps200, ps201 reception enabled reception clock detection clock start bit detection csie20 csck20 sck20/p20/ asck20 ss20/p25/ ti80 clock phase control reception detected internal clock output external clock input transmission and reception clock control baud rate generator note 4 tps203 tps202 tps201 tps200 csie20 csck20 f x /2-f x /2 8 baud rate generator control register 20 (brgc20) intst20 intsr20/intcsi20 internal bus figure 5-31. block diagram of serial interface 20 note see figure 5-32 for the configuration of the baud rate generator. port mode register (pm21)
preliminary product information 64 m m m m pd789166y, 789167y, 789176y, 789177y reception detection clock transmission shift clock reception shift clock reception detected txe20 rxe20 csie20 selector selector selector 1/2 1/2 transmission clock counter reception clock counter 4 f x /2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 2 sck20/asck20/p20 tps203 tps202 tps201 tps200 baud rate generator control register 20 (brgc20) internal bus figure 5-32. block diagram of baud rate generator 20
preliminary product information 65 m m m m pd789166y, 789167y, 789176y, 789177y (a) transmission shift register 20 (txs20) txs20 is a register in which transmission data is prepared. the transmission data is output from the txs20 bit-serially. when the data length is seven bits, bits 0 to 6 of the data in txs20 will be transmission data. writing data to txs20 triggers transmission. txs20 can be write-accessed, using an 8-bit memory manipulation instruction, but cannot be read- accessed. a reset input loads ffh into txs20. caution do not write to txs20 during transmission. txs20 and the reception buffer register 20 (rxb20) are mapped at the same address, such that any attempt to read from txs20 results in a value being read from the rxb. (b) reception shift register 20 (rxs20) rxs20 is a register in which serial data, received at the rxd20 pin, is converted to parallel data. once one entire byte has been received, rxs20 feeds the reception data to the reception buffer register 20 (rxb20). rxs20 cannot be manipulated directly by a program. (c) reception buffer register 20 (rxb20) rxb20 is used to hold reception data. once rxs20 has received one entire byte of data, it feeds that data into rxb20. when the data length is seven bits, the reception data is sent to bits 0 to 6 of rxb20, in which the msb is fixed to 0. rxb20 can be read-accessed, using an 8-bit memory manipulation instruction, but cannot be write- accessed. a reset input makes rxb20 undefined. caution rxb20 and the transmission shift register 20 (txs20) are mapped at the same address, such that any attempt to write to rxb20 results in a value being written to txs20. (d) transmission control circuit the transmission control circuit controls transmission. for example, it adds start, parity, and stop bits to the data in the transmission shift register 20 (txs20), according to the setting of the asynchronous serial interface mode register 20 (asim20). (e) reception control circuit the reception control circuit controls reception according to the setting of the asynchronous serial interface mode register 20 (asim20). it also checks for errors, such as parity errors, during reception. if an error is detected, the asynchronous serial interface status register 20 (asis20) is set according to the status of the error.
preliminary product information 66 m m m m pd789166y, 789167y, 789176y, 789177y (3) serial interface 20 control registers the following four types of registers are used to control serial interface 20. ? serial operation mode register 20 (csim20) ? asynchronous serial interface mode register 20 (asim20) ? asynchronous serial interface status register 20 (asis20) ? baud rate generator control register 20 (brgc20) (a) serial operation mode register 20 (csim20) csim20 is used to make the settings related to three-wire serial i/o mode. csim20 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears csim20 to 00h. figure 5-33. format of serial operation mode register 20 csie20 0 1 three-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address when reset r/w ff72h 00h r/w 76543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 three-wire serial i/o mode clock selection external clock pulse input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 three-wire serial i/o mode data phase selection outputs at the falling edge of sck20. outputs at the rising edge of sck20. ss20-pin selection functions of the ss20/p26 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 three-wire serial i/o mode clock phase selection clock is low active; sck20 is high in the idle state clock is high active; sck20 is low in the idle state cautions 1. bits 4 and 5 must be fixed to 0. 2. csim20 must be cleared to 00h, if uart mode is selected.
preliminary product information 67 m m m m pd789166y, 789167y, 789176y, 789177y (b) asynchronous serial interface mode register 20 (asim20) asim20 is used to make the settings related to serial interface 20 used in asynchronous serial interface mode. asim20 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears asim20 to 00h. figure 5-34. format of asynchronous serial interface mode register 20 txe20 0 1 transmission control txe20 rxe20 ps201 ps200 cl20 sl20 00 asim20 symbol address when reset r/w ff70h 00h r/w 76543210 transmission disabled transmission enabled rxe20 0 1 reception control reception disabled reception enabled ps201 0 0 1 1 parity bit specification ps200 0 1 0 1 no parity odd parity even parity at transmission, the parity bit is fixed to 0. at reception, a parity check is not made; no parity error is reported. cl20 0 1 transmission data character length specification 7 bits 8 bits sl20 0 1 transmission data stop bit length 1 bit 2 bits cautions 1. bits 0 and 1 must be fixed to 0. 2. if three-wire serial i/o mode is selected, asim20 must be cleared to 00h. 3. switch operation mode from one mode to another after stopping both serial transmission and reception.
preliminary product information 68 m m m m pd789166y, 789167y, 789176y, 789177y table 5-13. serial interface 20 operation mode settings (i) operation stopped mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 000 note 1 note 1 note 1 note 1 note 1 note 1 - - p22 p21 p20 other settings not to be set (ii) three-wire serial i/o mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 00100 1 note 2 note 2 011 msb external clock si20 note2 sck20 input 101 internal clock sck20 output 110 1 lsb external clock sck20 input 101 internal clock sck20 output other settings not to be set (iii) asynchronous serial interface mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 10000 note 1 note 1 011 lsb external clock p22 asck20 input note 1 note 1 internal clock p20 010001 note 1 note 1 1 external clock rxd20 p21 asck20 input note 1 note 1 internal clock p20 110001 011 external clock asck20 input note 1 note 1 internal clock p20 other settings not to be set notes 1. these pins can be used for port functions. 2. when only transmission is used, these pins can be used as p22 (cmos input/output). remark : dont care. first bit p20 pm20 p21 pm21 p22 pm22 p22/si20/ rxd20 pin function shift clock p21/so20/ txd20 pin function p20/sck20/ asck20 pin function shift clock shift clock first bit first bit p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function so20 (cmos output) txd20 (cmos output) txd20 (cmos output) p20 pm20 p21 pm21 p22 pm22 p20 pm20 p21 pm21 p22 pm22
preliminary product information 69 m m m m pd789166y, 789167y, 789176y, 789177y (c) asynchronous serial interface status register 20 (asis20) asis20 is used to display the type of a reception error, if it occurs while asynchronous serial interface mode is set. asis20 is manipulated using an 8-bit memory manipulation instruction. the contents of asis20 are undefined in three-wire serial i/o mode. a reset input clears asis20 to 00h. figure 5-35. format of asynchronous serial interface status register 20 pe20 0 1 parity error flag 00000 pe20 fe20 ove20 asis20 symbol address when reset r/w ff71h 00h r 76543210 no parity error has occurred. a parity error has occurred (parity mismatch in transmission data). fe20 0 1 framing error flag no framing error has occurred. a framing error has occurred (no stop bit detected). note 1 ove20 0 1 overrun error flag no overrun error has occurred. an overrun error has occurred note 2 (before data was read from the reception buffer register, the subsequent recepiton sequence was completed.) notes 1. even if 2 is specified for the number of stop bits (using bit 2 (sl20) of asim20), only one stop bit is detected at reception. 2. after an overrun occurs, read-access the reception buffer register 20 (rxb20). otherwise, the overrun error will recur each time data is received.
preliminary product information 70 m m m m pd789166y, 789167y, 789176y, 789177y (d) baud rate generator control register 20 (brgc20) brgc20 is used to specify the serial clock for serial interface 20. brgc20 is manipulated using an 8-bit memory manipulation instruction. a reset input clears brgc20 to 00h. figure 5-36. format of baud rate generator control register 20 tps203 0 0 0 0 0 0 0 0 1 3-bit counter source clock selection tps203 tps202 tps201 tps200 0000 brgc20 symbol address when reset r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 external clock pulse input at the asck20 pin note not to be set (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) other settings tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 - note an external clock can be used only in uart mode. cautions 1. any attempt to write to brgc20 during communication adversely affects the output of the baud rate generator, thus hampering normal operation. therefore, do not write to brgc20 during communication. 2. do not select n = 1 during operation at f x = 5.0 mhz, as n = 1 causes the rated baud rate to be exceeded. 3. when the external input clock is selected, set port mode register 2 (pm2) in input mode. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
preliminary product information 71 m m m m pd789166y, 789167y, 789176y, 789177y the transmission and reception clock pulses used to generate the baud rate are obtained by dividing the frequency of the main system clock pulse or a signal input to the asck20 pin. (i) generating transmission and reception clock pulses for baud rates based on the main system clock the frequency of the main system clock is divided to generate the transmission and reception clock pulses. the baud rate generated based on the main system clock is determined using the following expression. [baud rate] = [hz] f x : main system clock oscillation frequency table 5-14. relationships between main system clock frequencies and baud rates (example) error (%) f x = 5.0 mhz f x = 4.9152 mhz 1,200 8 70h 1.73 0 2,400 7 60h 4,800 6 50h 9,600 5 40h 19,200 4 30h 38,400 3 20h 76,800 2 10h caution do not select n = 1 during operation at f x = 5.0 mhz, as n = 1 causes the rated baud rate to be exceeded. baud rate (bps) n brgc20 setting f x 2 n+1 8
preliminary product information 72 m m m m pd789166y, 789167y, 789176y, 789177y (ii) generating transmission and reception clock pulses for baud rates based on an external clock pulse received at the asck20 pin the frequency of an external clock pulse received at the asck20 pin is used to generate the transmission and reception clock pulses. the baud rate generated based on the external clock pulse received at the asck20 pin is determined using the following expression. [baud rate] = [hz] f asck : frequency of clock pulse received at the asck20 pin table 5-15. relationships between asck20 pin input frequencies and baud rates (when brgc20 = 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 f asck 16
preliminary product information 73 m m m m pd789166y, 789167y, 789176y, 789177y 5.8.2 smb0 (system management bus) (1) smb0 functions smb0 has the following two types of modes. operation stopped mode smb mode (supporting multiple masters) (a) operation stopped mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (b) smb mode (supporting multiple masters) this mode is used for performing 8-bit data transmission to several devices, using a serial clock (scl0) line and a serial data bus (sda0) line. in this mode, which conforms to the smb format, start conditions, data, stop conditions can be output on the serial data bus during transmission. moreover, these data can be automatically detected by hardware during reception. in smb0, scl0 and sda0 are open-drain outputs, and therefore a pull-up resistor is required for the serial clock line and serial data bus line. i 2 c (inter ic) bus standard mode or high-speed mode can be specified by software in smb mode. figure 5-37 shows the block diagram of smb0.
preliminary product information 74 m m m m pd789166y, 789167y, 789176y, 789177y smb control register 0 (smbc0) acknowledge detection circuit start condi- tion detection circuit stop condi- tion detection circuit serial clock counter wakeup generator interrupt request signal generator prescaler smb clock selection register 0 (smbcl0) internal bus cld0 dad0 smc0 dfc0 cl01 cl00 smbe0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 internal bus figure 5-37. block diagram of smb0 tos02 tos01 tos00 svin0 lvl01 lvl00 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 + C + C f x /2 f x serial clock control circuit serial clock wait control circuit sclctl0 awtim0 scl0/ p23 sda0/ p24 n-ch open-drain output n-ch open-drain output selector selector slave address register 0 (smbsva0) smb shift register 0 (smb0) d q data hold time correc- tion circuit timeout count & control circuit scl ctl0 awtim0 stie0 toen0 tocl00 intsmbov0 intsmb0 tocl01 f x /2 6 f x /2 7 f x /2 8 f xt noise eliminator noise eliminator reference generator smb status register 0 (smb0) smb mode register 0 (smbm0) smb input level setting register 0 (smbvi0) cl00, cl01 acknowledge detection circuit exc0
preliminary product information 75 m m m m pd789166y, 789167y, 789176y, 789177y (2) smb0 configuration smb0 consists of the following hardware. table 5-16. smb0 configuration item configuration register smb shift register 0 (smb0) slave address register 0 (smbsva0) control register smb control register 0 (smbc0) smb status register 0 (smbs0) smb clock selection register 0 (smbcl0) smb mode register 0 (smbm0) smb input level setting register 0 (smbvi0) (a) smb shift register 0 (smb0) smb0 is a register that converts 8-bit serial data to 8-bit parallel data, and vice-versa. smb0 is used both for sending and receiving data. write and read operations for smb0 control actual send and receive operations. smb0 is manipulated with an 8-bit memory manipulation instruction. a reset input clears smb0 to 00h. (b) slave address register 0 (smbsva0) this register is used to set a local address when used as a slave. smbsva0 is manipulated with an 8-bit memory manipulation instruction. a reset input clears smbsva0 to 00h. (c) so latch the so latch is a latch that holds the sda0 pin output level. (d) wakeup control circuit this circuit generates an interrupt request when the address value set in slave address register 0 (smbsva0) and the received address match, or when an extension code is received. (e) clock selector selects the sampling clock to be used. (f) serial clock counter counts the serial clock output/input during send/receive operations, to check if 8-bit data has been sent or received.
preliminary product information 76 m m m m pd789166y, 789167y, 789176y, 789177y (g) interrupt request signal generation circuit controls the generation of interrupt request signals. smb interrupts are generated with the following two triggers. 8th clock or 9th clock of serial clock (set with wtim0 bit note ) generation of interrupt request at detection of stop condition (set with bit spie0 note ) note wtim0 bit: smb control register 0 (smbc0) bit 3 spie0 bit: smb control register 0 (smbc0) bit 4 (h) serial clock control circuit in master mode, generates the clock to be output to the scl0 pin from the sampling clock. (i) serial clock wait control circuit controls the wait timing. (j) acknowledge output circuit, stop condition detection circuit, start condition detection circuit, acknowledge detection circuit perform output and detection of control signals. (k) data hold time correction circuit generates the data hold time from the falling edge of the serial clock.
preliminary product information 77 m m m m pd789166y, 789167y, 789176y, 789177y (3) smb0 control registers the following five types of registers are used to control smb0. smb control register 0(smbc0) smb status register 0 (smbs0) smb clock selection register 0 (smbcl0) smb mode register 0 (smbm0) smb input level setting register 0 (smbvi0) the following additional registers are also used. smb shift register 0 (smb0) slave address register 0 (smbsva0) (a) smb control register 0 (smbc0) this register sets smb operation enable/disable, the wait timing, and other smb operations. smbc0 is manipulated with a 1-bit or 8-bit memory manipulation instruction. a reset input clears smbc0 to 00h. caution in smb mode, set port mode registers 2 (pm2 ) to achieve the following statuses. also, set each output latch to 0. p23 (scl0) is set to output mode (pm23 = 0). p24 (sda0) is set to output mode (pm24 = 0).
preliminary product information 78 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-38. format of smb control register 0 (1/4) smbe0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 smbc0 symbol address when reset r/w ff78h 00h r/w 654321 smbe0 0 1 clear conditions (smbe0 = 0) ? cleared with instruction ? cleared by reset input set conditions (smbe0 = 1) ? set with instruction smb operation operation disabled. presets extension register (smbs0). internal operation also disabled. operation enabled 7 0 lrel0 0 1 the standby status continues until the following communication participation conditions are met. ? startup as master after detection of stop condition ? matching addresses or extension code reception after start condition clear conditions (lrel0 = 0) note ? automatically cleared after execution ? cleared by reset input set conditions (lrel0 = 1) ? set with instruction escape from transmission normal operation escapes from the current transmission and enters the standby status. automatically cleared after execution. this bit is used when extension codes not relevant to the local station are received. the scl0 and sda0 lines enter the high impedance status. the following flags are cleared. ? std0 ? stt0 ? spt0 ? ackd0 ? trc0 ? coi0 ? exc0 ? msts0 wrel0 0 1 clear conditions (wrel0 = 0) note ? automatically cleared after execution ? cleared by reset input set conditions (wrel0 = 1) ? set with instruction wait cancel does not cancel wait. cancels wait. automatically cleared after wait cancellation. spie0 0 1 clear conditions (spie0 = 0) note ? cleared with instruction ? cleared by reset input set conditions (spie0 = 1) ? set with instruction interrupt request generation at stop condition detection disabled enabled note this flag's signals are made invalid by setting smbe0 = 0.
preliminary product information 79 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-38. format of smb control register 0 (2/4) wtim0 0 1 the setting of this bit becomes invalid during address transmission, and becomes effective at the end of transmission. during operation as master, a wait is inserted at the falling edge of the 9th clock during address transmission. a slave that receives a local address enters the wait status at the falling edge of the 9th clock after generation of an acknowledge. a slave that receives an extension code enters the wait status at the falling edge of the 8th clock. clear conditions (wtim0 = 0) note ? cleared with instruction ? cleared by reset input set conditions (wtim0 = 1) ? set with instruction wait and interrupt request generation control generates interrupt request at falling edge of 8th clock. in case of master: waits with clock output at low level after 8 clocks have been output. in case of slave: waits master with clock set to low level after 8 clocks have been input. generates interrupt request at falling edge of 9th clock. in case of master: waits with clock at low level after 9 clocks have been output. in case of slave: waits master with clock set at low level after 9 clocks have been input. acke0 0 1 clear conditions (acke0 = 0) note ? cleared with instruction ? cleared by reset input set conditions (acke0 = 1) ? set with instruction acknowledge control acknowledge disabled acknowledge enabled. sda0 line set to low level during 9 clocks. however, invalid during address transmission, and valid when exc0 = 1. note this flag's signals are made invalid by setting smbe0 = 0.
preliminary product information 80 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-38. format of smb control register 0 (3/4) cautions regarding set timing ? master receive operation: setting during transmission is prohibited. set acke0 = 0; can be set only after end of receive operation has been notifi ed to slave. ? master send operation: note that start condition may not be generated normally during ack period. ? setting at the same time as spt0 is prohibited. stt0 0 1 clear conditions (stt0 = 0) note ? cleared with instruction ? cleared upon defeat in arbitration ? cleared after generation of start condition by master ? cleared by reset input set conditions (stt0 = 1) ? set with instruction start condition trigger doesn't generate start condition. when bus is released (stop status): generates start conditions (activation as master). changes sda0 line from high level to low level and generates start condition. then secures rated time and sets scl0 to low level. when not participating on bus: functions as start condition reservation flag. when set, automatically generates start condition after bus is released. note this flag's signals are made invalid by setting smbe0 = 0.
preliminary product information 81 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-38. format of smb control register 0 (4/4) cautions regarding set timing master receive operation: setting during transmission is prohibited. set acke0 = 0; can be set only after end of receive operation has been notified to slave. master send operation: note that stop condition may not be generated normally during ack period. setting at the same time as stt0 is prohibited. set spt0 only during operation as master. note 1 note that when wtim0 = 0, if spt0 is set during the wait period after 8-clock output, a stop condition is generated during the high-level period of the 9th clock following wait release. if it is necessary to output a 9th clock, change the setting of wtim0 from 0 to 1 during the wait period following 8-clock output, and set spt0 during the wait period following the 9th clock output. spt0 0 1 clear conditions (spt0 = 0) note 2 cleared with instruction cleared upon defeat in arbitration cleared automatically after detection of stop condition cleared by reset input set conditions (spt0 = 1) set with instruction stop condition trigger does not generate stop condition. generates stop condition (end transmission as master). after setting sda0 line to low level, sets scl0 line to high level, or maintains scl0 line at high level. then, secures rated time, changes sda0 line from low level to high level, and generates stop condition. notes 1. set stp0 only during operation as master. however, for master operation by the time a stop condition is detected for the first time following operation enable, spt0 must be set once to generate a stop condition. 2. this flag's signals are made invalid by setting smbe0 = 0. caution while smb status register 0 (smbs0) bit 3 (trc0) = 1, when wrel0 is set at the 9th clock and wait is released, trc0 is cleared and the sda0 line is placed in high impedance. remark std0 : smb status register 0 (smbs0) bit 1 ackd0 : smb status register 0 (smbs0) bit 2 trc0 : smb status register 0 (smbs0) bit 3 coi0 : smb status register 0 (smbs0) bit 4 exc0 : smb status register 0 (smbs0) bit 5 msts0 : smb status register 0 (smbs0) bit 7
preliminary product information 82 m m m m pd789166y, 789167y, 789176y, 789177y (b) smb status register 0 (smbs0) this register indicates the smb status. smbs0 is manipulated with a 1-bit or 8-bit memory manipulation instruction. smbs0 is a read-only register. a reset input clears smbs0 to 00h. figure 5-39. format of smb status register 0 (1/3) msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 smbs0 symbol address when reset r/w ff79h 00h r msts0 0 1 clear conditions (msts0 = 0) cleared upon detection of stop condition cleared when ald0 = 1 cleared when lrel0 = 1 cleared when smbe0 changes from 1 to 0 cleared by reset input set conditions (msts0 = 1) set during generation of start condition master status slave status or communication wait status master transmission status exc0 0 1 clear conditions (exc0 = 0) cleared upon detection of start condition cleared upon detection of stop condition cleared when lrel0 = 1 cleared when smbe0 changes from 1 to 0 cleared by reset input extension code receive detection does not receive extension code. receives extension code. ald0 0 1 clear conditions (ald0 = 0) automatically cleared after reading smbs0 note cleared when smbe0 changes from 1 to 0 cleared by reset input set conditions (ald0 = 1) set upon defeat in arbitration arbitration defeat detection no arbitration, or won in arbitration. defeated in arbitration. msts0 cleared. set conditions (exc0 = 1) set when high-order 4 bits of received address are 0000 or 1111 (set at rising edge of 8th clock) 654321 7 0 note the bit is also cleared when a bit manipulation instruction is executed for any of other bit of smbs0.
preliminary product information 83 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-39. format of smb status register 0 (2/3) coi0 0 1 clear conditions (coi0 = 0) cleared upon detection of start condition cleared upon detection of stop condition cleared when lrel0 = 1 cleared when smbe0 changes from 1 to 0 cleared by reset input set conditions (coi0 = 1) set when received address matches local address (sva0) (set at rising edge of 8th clock) matching address detection address does not match. address matches. ackd0 0 1 clear conditions (ackd0 = 0) cleared upon detection of stop condition cleared at rising edge of 1st clock of following byte cleared when lrel0 = 1 acknowledge output does not detect acknowledge. detects acknowledge. cleared when smbe0 changes from 1 to 0 cleared by reset input trc0 0 1 clear conditions (trc0 = 0) cleared upon detection of stop condition cleared when lrel0 = 1 cleared smbe0 changes from 1 to 0 cleared when wrel0 = 1 cleared when ald0 changes from 0 to 1 cleared by reset input in case of master: when "1" is output to 1st byte lsb (transmission direction specification bit) in case of slave: upon detection of start condition in case of non-participation in communication receive/send status detection receive status (when not in send status). sets sda0 line to high impedance. send status. sets so that so latch value can be output to sda0 line (valid from falling edge of 9th clock of 1st byte). set conditions (trc0 = 1) in case of master: upon generation of start condition in case of slave: when "1" is input to 1st byte lsb (transmission direction specification bit) set conditions (ackd0 = 1) set when sda0 line is low level at rising edge of 9th clock of scl0
preliminary product information 84 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-39. format of smb status register 0 (3/3) std0 0 1 clear conditions (std0 = 0) cleared upon detection of stop condition cleared at rising edge of 1st clock of byte following address transmission cleared when lrel0 = 1 cleared when smbe0 changes from 1 to 0 cleared by reset input set conditions (std0 = 1) set upon detection of start condition start condition detection does not detect start condition. detects start condition. indicates that address transmission is in progress. spd0 0 1 clear conditions (spd0 = 0) cleared at rising edge of 1st clock of address transfer byte following detection of start condition after this bit has been set cleared when smbe0 changes from 1 to 0 cleared by reset input stop condition detection does not detect stop condition. detects stop condition. transmission by master is completed and bus is released. set conditions (spd0 = 1) set upon detection of stop condition remark lrel0 : smb control register 0 (smbc0) bit 6 smbe0 : smb control register 0 (smbc0) bit 7
preliminary product information 85 m m m m pd789166y, 789167y, 789176y, 789177y (c) smb clock selection register 0 (smbcl0) this register sets the smb transmission clock. smbcl0 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears smbcl0 to 00h. figure 5-40. format of smb clock selection register 0 (1/2) 0 0 cld0 dad0 smc0 dfc0 cl01 cl00 smbcl0 symbol address when reset r/w ff7ah 00h r/w note 1 654321 cld0 0 1 clear conditions (cld0 = 0) cleared when scl0 line is low level cleared when smbe0 = 0 cleared by reset input set conditions (cld0 = 1) set when scl0 line is high level scl0 line level detection (valid only when smbe0 = 1) detects that scl0 line is low level. detects that scl0 line is high level. 7 0 dad0 0 1 clear conditions (dad0 = 0) cleared when sda0 line is low level cleared when smbe0 = 0 cleared by reset input set conditions (dad0 = 1) set when sda0 line is high level sda0 line level detection (valid only when smbe0 = 1) detects that sda0 line is low level. detects that sda0 line is high level. smc0 0 1 clear conditions (smc0 = 0) cleared with instruction cleared by reset input set conditions (smc0 = 1) set with instruction operating mode switching iic standard mode or smb mode operation iic high-speed mode dfc0 0 1 digital filter operation control note 2 digital filter off digital filter on notes 1. bits 4 and 5 are read-only. 2. the digital filter can be used in the high-speed mode. when used in the high-speed mode, the digital filter provides a slower response.
preliminary product information 86 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-40. format of smb clock selection register 0 (2/2) cl01 0 0 1 1 cl00 0 1 0 1 selection clock f x note 1 f x f x /2 not to be set smb/standard mode high-speed mode f x note 2 f x /2 note 2 notes 1. available range: 1.0 mhz f x 4.19 mhz 2. available range: f x 3 2.0 mhz caution bits 6 and 7 must be fixed to 0. remark f x : main system clock oscillation frequency
preliminary product information 87 m m m m pd789166y, 789167y, 789176y, 789177y (d) smb mode register 0 (smbm0) smbm0 is used to specify scl0 level control and interrupt control. smbm0 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input loads 20h into smbm0. figure 5-41. format of smb mode register 0 (1/2) sclctl0 scl level control note 1 scl0 is held low. 0 0 0 sclctl0 awtim0 stie0 toen0 tocl01 tocl00 smbm0 symbol address when reset r/w ff7ch 20h r/w 6 7543 2 awtim0 at the slave, an interrupt request is generated on the falling edge of the 9th clock period when an address match (coi0 = 1) is found during address data reception. the clock is pulled low to cause the master to wait. 0 1 0 when scl0 is high, scl0 is held low after waiting until scl0 is made low. normal operation 1 stie0 start condition interrupt enable start condition interrupt generation is disabled. 0 normal operation 1 wait and interrupt control when an address match is found notes 2, 3 at the slave, an interrupt request is generated on the falling edge of the 8th clock period when an address match (coi0 = 1) is found during address data reception. the clock is pulled low to cause the master to wait. 1 notes 1. if scl0 is made low with sclctl0, wait state cannot be released with wrel0. 2. when an extension code is received (exc0 = 1), wait state is forcibly set in the 8th clock period. 3. during address transfer, the master waits in the 9th clock period.
preliminary product information 88 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-41. format of smb mode register 0 (2/2) toen0 time-out count enable bit note the time-out count is cleared to 0, then count operation is disabled. 0 1 tocl00 tocl01 time-out clock selection bits f x /2 6 0 1 0 1 0 0 1 1 time-out count operation is enabled. (78.125 khz) f x /2 7 (39.063 khz) f x /2 8 (19.531 khz) f xt (32.768 khz) note an interrupt (intsmbov0) is generated when the time-out counter overflows. the hardware does not reset smb operation. ensure that smb operation is reset by software after intsmbov0 generation. caution bits 6 and 7 must be fixed to 0. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
preliminary product information 89 m m m m pd789166y, 789167y, 789176y, 789177y (e) smb input level setting register 0 (smbvi0) smbvi0 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears smbvi0 to 00h. figure 5-42. format of smb input level setting register 0 tos02 0 tos02 tos01 tos00 svin0 0 lvl01 lvl00 smbvi0 symbol address when reset r/w ff7dh 00h r/w 6 7543 2 1 0 svin0 input level selection bit same input level as the ordinary hysteresis 0 the voltage set with lvl01 and lvl00 is used as the scl0 and sda0 input level threshold. 1 lvl01 lvl00 input level selection bits note the input level is 0.1875 v dd . the input level is 0.25 v dd . the input level is 0.375 v dd . the input level is 0.5 v dd . 0 0 1 1 0 1 0 1 tos01 tos00 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1,024/f to (13.1 ms) 896/f to (11.5 ms) f to = f x /2 6 f to = f x /2 7 f to = f x /2 8 f to = f xt 768/f to (9.8 ms) 640/f to (8.2 ms) 512/f to (6.6 ms) 384/f to (4.9 ms) 256/f to (3.3 ms) 128/f to (1.6 ms) 1,024/f to (26.2 ms) 896/f to (22.9 ms) 768/f to (19.7 ms) 640/f to (16.4 ms) 512/f to (13.1 ms) 384/f to (9.8 ms) 256/f to (6.6 ms) 128/f to (3.2 ms) 1,024/f to (52.4 ms) 896/f to (45.9 ms) 768/f to (39.3 ms) 640/f to (32.8 ms) 512/f to (26.2 ms) 384/f to (19.7 ms) 256/f to (13.1 ms) 128/f to (6.6 ms) 1,024/f to (31.3 ms) 896/f to (27.3 ms) 768/f to (23.4 ms) 640/f to (19.5 ms) 512/f to (15.6 ms) 384/f to (11.7 ms) 256/f to (7.8 ms) 128/f to (3.9 ms) time-out time setting bits note set an input level from 0.75 to 1.25 v. caution bits 2 and 7 must be fixed to 0. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f to : clock selected using bits 0 and 1 (tocl00, tocl01) of smb mode register 0 (smbm0) 4. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
preliminary product information 90 m m m m pd789166y, 789167y, 789176y, 789177y (f) smb shift register 0 (smb0) this register is used to perform serial send/receive (shift operation) in synchronization with the serial clock. read/write operations can be performed in 8-bit units, but do not write data to the smb0 during transmission. smb0 symbol address when reset r/w ff1bh 00h r/w 6543 21 7 0 (g) smb slave address register 0 (smbsva0) this register stores the smb slave address. it can be read/written in 8-bit units, but bit 0 is fixed to 0. smbsva0 symbol address when reset r/w ff7bh 00h r/w 6 543 21 7 0 0
preliminary product information 91 m m m m pd789166y, 789167y, 789176y, 789177y 5.9 multiplier 5.9.1 multiplier function the multiplier enables a calculation of 8 bits 8 bits = 16 bits. 5.9.2 multiplier configuration (1) multiplication result storage register 0 (mul0) this register stores 16-bit multiplication results. this register holds the result of a multiplication after 16 cpu clock periods. mul0 is manipulated using a 16-bit memory manipulation instruction. a reset input makes mul0 undefined. caution mul0 is designed to be manipulated using a 16-bit memory manipulation instruction. it can also be manipulated using 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is used to set mul0, it must be in a direct addressing access mode. (2) multiplication data registers a and b (mra0, mrb0) these registers store 8-bit multiplication data. the multiplier multiplies the value of mra0 by the value of mrb0. mra0 and mrb0 are set using an 8-bit memory manipulation instruction. a reset input makes these registers undefined. figure 5-43 shows the block diagram of the multiplier.
preliminary product information 92 m m m m pd789166y, 789167y, 789176y, 789177y figure 5-43. block diagram of multiplier clear start internal bus internal bus multiplication data register a (mra0) multiplication data register b (mrb0) selector counter value 3-bit counter cpu clock counter output 16-bit adder 16-bit multiplication result storage register (master) (mul0) 16-bit multiplication result storage register (slave) reset multiplier control register (mulc0) 0000000 mulst0 3
preliminary product information 93 m m m m pd789166y, 789167y, 789176y, 789177y 5.9.3 multiplier control register the following register is used to control the multiplier: multiplier control register 0 (mulc0) mulc0 not only controls operations, but also indicates the operation status of the multiplier. mulc0 is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears mulc0 to 00h. figure 5-44. format of multiplier control register 0 (mulc0) 0 0 0 0 0 0 0 mulst0 mulc0 symbol address when reset r/w ffd2h 00h r/w 6 7543 2 1 0 mulst0 0 1 multiplier operation start control bit operation is stopped after the counter is cleared to 0. operation is stopped. multiplier operation status operation is enabled. operation is being executed. caution bits 1 to 7 must be fixed to 0.
preliminary product information 94 m m m m pd789166y, 789167y, 789176y, 789177y 6. interrupt functions 6.1 interrupt function types two types of interrupt function are supported. (1) nonmaskable interrupt a nonmaskable interrupt request is accepted unconditionally, that is, even when interrupts are disabled. a nonmaskable interrupt takes precedence over all other interrupts; it is not subjected to interrupt priority control. a nonmaskable interrupt causes the standby release signal to be generated. the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y support one nonmaskable interrupt source namely, the watchdog timer interrupt. (2) maskable interrupt maskable interrupts are those which are subjected to mask control. if two or more maskable interrupts occur simultaneously, the default priority listed in table 6-1 applies. the maskable interrupts cause the standby release signal to be generated. the maskable interrupts supported by the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y include 4 external interrupt sources and 12 internal interrupt sources. 6.2 interrupt sources and configuration the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y each support a total of 17 maskable and nonmaskable interrupt sources. (see table 6-1 .)
preliminary product information 95 m m m m pd789166y, 789167y, 789176y, 789177y table 6-1. interrupt sources interrupt type priority note 1 interrupt source internal/external name trigger nonmaskable interrupt - intwdt watchdog timer overflow (when watchdog timer mode 1 is selected) internal 0004h (a) maskable interrupt 0 intwdt watchdog timer overflow (when the interval timer mode is selected) (b) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intsr20 end of uart reception on serial interface 20 internal 000eh (b) intcsi20 end of three-wire sio transfer reception on serial interface 20 6 intst20 end of uart transmission on serial interface 20 0010h 7 intwt clock timer interrupt 0012h 8 intwti interval timer interrupt 0014h 9 inttm80 generation of match signal for 8-bit timer/event counter 80 0016h 10 inttm81 generation of match signal for 8-bit timer/event counter 81 0018h 11 inttm82 generation of match signal for 8-bit timer counter 82 001ah 12 inttm90 generation of match signal for 16-bit timer counter 90 001ch 13 intsmb0 system management bus interrupt 001eh 14 intsmbov0 system management bus time- out interrupt 0020h 15 intad0 a/d conversion completion signal 0022h notes 1. the priority regulates which maskable interrupt is higher, when two or more maskable interrupts are requested simultaneously. zero signifies the highest priority, while 15 is the lowest. 2. basic configuration types (a), (b), and (c) correspond to (a), (b), and (c) in figure 6-1, respectively. vector table address basic configuration type note 2
preliminary product information 96 m m m m pd789166y, 789167y, 789176y, 789177y figure 6-1. basic configuration of interrupt functions (a) internal nonmaskable interrupt internal bus interrupt request vector table address generation circuit standby release signal (b) internal maskable interrupt internal bus mk if interrupt request ie vector table address generation circuit standby release signal (c) external maskable interrupt internal bus external interrupt mode register (intm0, intm1) mk if ie vector table address generation circuit standby release signal edge detection circuit interrupt request if : interrupt request flag ie : interrupt enable flag mk : interrupt mask flag
preliminary product information 97 m m m m pd789166y, 789167y, 789176y, 789177y 6.3 interrupt function control registers the interrupt functions are controlled by the following registers. ? interrupt request flag registers (if0 and if1) ? interrupt mask flag registers (mk0 and mk1) ? external interrupt mode registers (intm0 and intm1) ? program status word (psw) table 6-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags. table 6-2. interrupt request signals and corresponding flags interrupt request signal interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intp3 intsr20/intcsi20 intst20 intwt intwti inttm80 inttm81 inttm82 inttm90 intsmb0 intsmbov0 intad0 tmif4 pif0 pif1 pif2 pif3 srif20 stif20 wtif wtifi tmif80 tmif81 tmif82 tmif90 smbif0 smbovif0 adif0 tmmk4 pmk0 pmk1 pmk2 pmk3 srmk20 stmk20 wtmk wtmki tmmk80 tmmk81 tmmk82 tmmk90 smbmk0 smbovmk0 admk0
preliminary product information 98 m m m m pd789166y, 789167y, 789176y, 789177y (1) interrupt request flag registers (if0 and if1) an interrupt request flag is set (1), when the corresponding interrupt request is issued, or when the related instruction is executed. it is cleared (0), when the interrupt request is accepted, when a reset signal is input, or when a related instruction is executed. if0 and if1 are manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears if0 and if1 to 00h. figure 6-2. format of interrupt request flag register adif0 smbovif0 smbif0tmif90 tmif82 tmif81 tmif80 wtiif if1 ffe1h 00h r/w xxifx 0 1 interrupt request flag no interrupt request signal has been issued. an interrupt request signal has been issued; an interrupt request has been made. 6 7 543210 wtif stif20srif20 pif3 pif2 pif1 pif0 tmif4 if0 symbol address when reset r/w ffe0h 00h r/w 6 7 543210 cautions 1. the tmif4 flag can be read- and write-accessed only when the watchdog timer is being used as an interval timer. it must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 2. when port 3 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. to use port 3 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
preliminary product information 99 m m m m pd789166y, 789167y, 789176y, 789177y (2) interrupt mask flag registers (mk0 and mk1) the interrupt mask flags are used to enable and disable the corresponding maskable interrupts. mk0 and mk1 are manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input loads ffh into mk0 and mk1. figure 6-3. format of interrupt mask flag register admk0 smbovmk0 smbmk0 tmmk90 tmmk82 tmmk81 tmmk80 wtimk mk1 ffe5h ffh r/w xxmkx 0 1 interrupt handling control enable interrupt handling. disable interrupt handling. 6 7 543210 wtmk srmk20 stmk20 pmk3 pmk2 pmk1 pmk0 tmmk4 mk0 symbol address when reset r/w ffe4h ffh r/w 6 7 543210 cautions 1. when the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read tmmk4 flag results in an undefined value being detected. 2. when port 3 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. to use port 3 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
preliminary product information 100 m m m m pd789166y, 789167y, 789176y, 789177y (3) external interrupt mode register 0 (intm0) intm0 is used to specify an effective edge for intp0 to intp2. intm0 is manipulated using an 8-bit memory manipulation instruction. a reset input clears intm0 to 00h. figure 6-4. format of external interrupt mode register 0 es21 es20 es11 es10 es01 es00 0 0 intm0 76543210 es11 0 0 1 1 intp1 effective edge selection es10 0 1 0 1 falling edge rising edge not to be set both rising and falling edges es21 0 0 1 1 intp2 effective edge selection es20 0 1 0 1 falling edge rising edge not to be set both rising and falling edges es01 0 0 1 1 intp0 effective edge selection es00 0 1 0 1 falling edge rising edge not to be set both rising and falling edges symbol address when reset r/w ffech 00h r/w cautions 1. bits 0 and 1 must be fixed to 0. 2. before setting intm0, set the corresponding interrupt mask flag register to 1 to disable interrupts. to enable interrupts, clear (0) the corresponding interrupt request flag, then the corresponding interrupt mask flag register.
preliminary product information 101 m m m m pd789166y, 789167y, 789176y, 789177y (4) external interrupt mode register 1 (intm1) intm1 is used to specify an effective edge for intp3. intm1 is manipulated using an 8-bit memory manipulation instruction. a reset input clears intm1 to 00h. figure 6-5. format of external interrupt mode register 1 00 0 0 es31 0 0 es30 intm1 7 654 32 10 es31 0 0 1 1 intp3 effective edge selection es30 0 1 0 1 falling edge rising edge not to be set both rising and falling edges symbol address when reset r/w ffedh 00h r/w cautions 1. bits 2 to 7 must be fixed to 0. 2. before setting intm1, set the corresponding interrupt mask flag register to 1 to disable interrupts. to enable interrupts, clear (0) the corresponding interrupt request flag, then the corresponding interrupt mask flag register.
preliminary product information 102 m m m m pd789166y, 789167y, 789176y, 789177y (5) program status word (psw) the program status word is used to hold the instruction execution result and the current status of the interrupt requests. the ie flag, used to enable and disable maskable interrupts, is mapped to the psw. the psw can be read- and write-accessed in 8-bit units, as well as in 1-bit units when using bit manipulation instructions and dedicated instructions (ei and di). when a vector interrupt is accepted, the psw is automatically saved to a stack, and the ie flag is reset (0). a reset input loads 02h into the psw. figure 6-6. program status word configuration ie z 0 ac 0 0 1 cy psw symbol when reset 02h 76543210 ie 0 1 disable enable whether to enable/disable interrupt acceptance used in the execution of ordinary instructions
preliminary product information 103 m m m m pd789166y, 789167y, 789176y, 789177y 7. standby function 7.1 standby function the standby function is supported to minimize the systems power consumption. there are two standby modes: halt and stop. halt and stop modes are selected using the halt and stop instructions, respectively. (1) halt mode in halt mode, the cpu clock is stopped. interleaving normal mode with halt mode can reduce the average power consumption. (2) stop mode in stop mode, the main system clock is stopped. as a result, main system clock-based operation is also stopped, thus minimizing power consumption. caution before shifting to stop mode, first stop the operation of the hardware, then execute the stop instruction.
preliminary product information 104 m m m m pd789166y, 789167y, 789176y, 789177y table 7-1. operation statuses in halt mode item halt mode operation status while the main system clock is running halt mode operation status while the subsystem clock is running while the subsystem clock is running while the subsystem clock is not running while the main system clock is running while the main system clock is not running clock generator can operate with the main system clock. does not run. cpu operation disabled port (output latch) remains in the state existing before the selection of halt mode. 16-bit timer counter (tm90) operation enabled operation enabled note 1 operation enabled operation enabled note 2 8-bit timer/event counter (tm80) operation enabled operation enabled note 3 8-bit timer/event counter (tm81) operation enabled operation enabled note 4 8-bit timer counter (tm82) operation enabled operation enabled note 1 operation enabled operation enabled note 2 clock timer operation enabled operation enabled note 1 operation enabled operation enabled note 2 watchdog timer operation enabled operation disabled serial interface operation enabled operation enabled note 5 smb operation enabled operation enabled note 6 a/d converter operation disabled multiplier operation disabled external interrupt operation enabled note 7 notes 1. operation is enabled while the main system clock is selected. 2. operation is enabled while the subsystem clock is selected. 3. operation is enabled only when ti80 is selected as the count clock. 4. operation is enabled only when ti81 is selected as the count clock. 5. operation is enabled in both three-wire serial i/o and uart modes while an external clock is being used. 6. while in slave mode, an interrupt can be generated when an address match is found. 7. maskable interrupt that is not masked
preliminary product information 105 m m m m pd789166y, 789167y, 789176y, 789177y table 7-2. operation statuses in stop mode item stop mode operation status while the main system clock is running while the subsystem clock is running while the subsystem clock is not running clock generator does not operate with the main system clock. cpu operation disabled port (output latch) remains in the state existing before the selection of stop mode. 16-bit timer counter (tm90) operation enabled note 1 operation disabled 8-bit timer/event counter (tm80) operation enabled note 2 8-bit timer/event counter (tm81) operation enabled note 3 8-bit timer counter (tm82) operation enabled note 1 operation disabled clock timer operation enabled note 1 operation disabled watchdog timer operation disabled serial interface operation enabled note 4 smb operation enabled note 5 a/d converter operation disabled multiplier operation disabled external interrupt operation enabled note 6 notes 1. operation is enabled while the subsystem clock is selected. 2. operation is enabled only when ti80 is selected as the count clock. 3. operation is enabled only when ti81 is selected as the count clock. 4. operation is enabled in both three-wire serial i/o and uart modes while an external clock is being used. 5. while in slave mode, an interrupt can be generated when an address match is found. 6. maskable interrupt that is not masked
preliminary product information 106 m m m m pd789166y, 789167y, 789176y, 789177y 7.2 standby function control register the oscillation settling time selection register (osts) is used to control the wait time, from the time stop mode is deselected by an interrupt request, until oscillation settles. the osts is manipulated using an 8-bit memory manipulation instruction. a reset input loads 04h into the osts. if a reset input is used to deselect stop mode, the time required for oscillation to settle will be 2 15 /f x , rather than 2 17 /f x . figure 7-1. format of oscillation settling time selection register osts2 osts1 osts0 osts symbol address when reset r/w fffah 04h r/w 76543210 oscillation settling time selection osts2 0 0 1 osts1 0 1 0 0000 osts0 0 0 0 2 12 /fx 2 15 /fx 2 17 /fx not to be set (819 s) (6.55 ms) (26.2 ms) m other settings 0 caution the wait time required to deselect stop mode does not include the time (a in the following figure) required for the clock oscillation to settle after stop mode is deselected, regardless of whether stop mode is deselected by a reset input or interrupt. stop mode release x1 pin voltage waveform v ss a remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
preliminary product information 107 m m m m pd789166y, 789167y, 789176y, 789177y 8. reset functions the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y can be reset using the following signals. (1) external reset signal input to the reset pin (2) internal reset signal generated upon the elapse of the period set in the watchdog timer, used for detecting an unintended program loop the external and internal reset signals are functionally equivalent. when reset is input, they cause program execution to begin at the addresses indicated at addresses 0000h and 0001h, respectively. if a low level signal is applied to the reset pin, or if the watchdog timer overflows, a reset occurs, causing each piece of the hardware to enter the states listed in table 8-1. while a reset signal is being input, or while the oscillation frequency is settling immediately after the end of a reset sequence, each pin remains in the high- impedance state. if a high level signal is applied to the reset pin, a reset sequence is terminated, and program execution begins once the oscillation settling time (2 15 /f x ) elapses. a watchdog timer overflow-based reset sequence is terminated automatically. similarly, program execution begins upon the elapse of the oscillation settling time (2 15 /f x ). cautions 1. to use an external reset sequence, supply a low level signal to the reset pin and maintain the signal for at least 10 m m m m s. 2. when a reset is used to deselect stop mode, the information related to stop mode is held during the reset sequence, that is, while the reset signal is applied. the port pins remain in the high-impedance state, however. figure 8-1. reset function block diagram reset count clock reset control circuit watchdog timer stop over- flow reset signal interrupt function
preliminary product information 108 m m m m pd789166y, 789167y, 789176y, 789177y table 8-1. state of the hardware after a reset (1/2) hardware state after reset program counter (pc) note 1 loaded with the contents of the reset vector table (0000h, 0001h) stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general-purpose register undefined note 2 ports (p0 to p3, p5, p6) (output latch) 00h port mode registers (pm0 to pm3, pm5) ffh pull-up resistor option registers (pu0, pub2, pub3) 00h processor clock control register (pcc) 02h suboscillation mode register (sckm) 00h subclock control register (css) 00h oscillation settling time selection register (osts) 04h 16-bit timer/counter 90 timer register (tm90) 0000h compare register (cr90) ffffh capture register (tcp90) undefined mode control register (tmc90) 00h buzzer output control register (bzc90) 00h timer registers (tm80 to tm82) 00h compare registers (cr80 to cr82) undefined mode control registers (tmc80 to tmc82) 00h clock timer mode control register (wtm) 00h watchdog timer timer clock selection register (tcl2) 00h mode register (wdtm) 00h a/d converter mode register (adm0) 00h a/d input selection register (ads0) 00h a/d conversion result register (adcr0) undefined serial interface 20 mode register (csim20) 00h asynchronous serial interface mode register (asim20) 00h asynchronous serial interface status register (asis20) 00h baud rate generator control register (brgc20) 00h transmission shift register (txs20) ffh reception buffer register (rxb20) undefined notes 1. while a reset signal is being input, and during the oscillation settling period, the contents of the pc will be undefined, while the remainder of the hardware will be the same as after the reset. 2. in standby mode, the ram enters the hold state after a reset. 8-bit timer/event counters 80 to 82
preliminary product information 109 m m m m pd789166y, 789167y, 789176y, 789177y table 8-1. state of the hardware after a reset (2/2) hardware state after reset smb0 control register (smbc0) 00h status register (smbs0) 00h clock selection register (smbcl0) 00h slave address register (smbsva0) 00h mode register (smbm0) 20h input level setting register (smbvi0) 00h shift register (smb0) 00h multiplier 16-bit multiplication result storage register (mul0) undefined multiplication data register (mra0, mrb0) undefined multiplier control register (mulc0) 00h interrupts request flag registers (if0, if1) 00h mask flag registers (mk0, mk1) ffh external interrupt mode registers (intm0, intm1) 00h
preliminary product information 110 m m m m pd789166y, 789167y, 789176y, 789177y 9. mask options the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y have the following mask options. ? mask option for p50 to p53 this option is used to specify whether to incorporate a pull-up resistor, as follows: <1> to indicate whether a pull-up resistor is to be incorporated, an individual bit is specified, independently of the other bits. <2> the specification of each bit indicates that a pull-up resistor is not to be incorporated.
preliminary product information 111 m m m m pd789166y, 789167y, 789176y, 789177y 10. instruction set overview the instruction set for the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y is listed later. 10.1 legend 10.1.1 operand formats and descriptions the description made in the operand field of each instruction conforms to the operand format for the instructions listed below (the details conform with the assembly specification). if more than one operand format is listed for an instruction, one is selected. uppercase letters, #, !, $, and a pair of [ and ] are used to specify keywords, which must be written exactly as they appear. the meanings of these special characters are as follows: #: immediate data specification $: relative address specification !: absolute address specification [ and ]: indirect address specification immediate data should be described using appropriate values or labels. the specification of values and labels must be accompanied by #, !, $, or a pair of [ and ]. operand registers, expressed as r or rp in the formats, can be described using both functional names (x, a, c, etc.) and absolute names (r0, r1, r2, and other names listed in table 11-1). table 10-1. operand formats and descriptions format description r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh: immediate data or label fe20h to ff1fh: immediate data or label (even addresses only) addr16 addr5 0000h to ffffh: immediate data or label (only even address for 16-bit data transfer instructions) 0040h to 007fh: immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark for the special function register symbols, see table 4-1 .
preliminary product information 112 m m m m pd789166y, 789167y, 789176y, 789177y 10.1.2 descriptions of the operation field a : a register (8-bit accumulator) x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair (16-bit accumulator) bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag ie : interrupt request enable flag nmis : flag to indicate that a nonmaskable interrupt is being handled () : contents of a memory location indicated by a parenthesized address or register name x h , x l : upper and lower 8 bits of a 16-bit register ^ : logical product (and) : logical sum (or) : exclusive or ? : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 10.1.3 description of the flag operation field (blank) : no change 0 : to be cleared to 0 1 : to be set to 1 : to be set or cleared according to the result r : to be restored to the previous value
preliminary product information 113 m m m m pd789166y, 789167y, 789176y, 789177y 10.2 operations mnemonic operand byte clock operation flag zaccy mov r, #byte 3 6 r ? byte saddr, #byte 3 6 (saddr) ? byte sfr, #byte 3 6 sfr ? byte a, r note 1 24a ? r r, a note 1 24r ? a a, saddr 2 4 a ? (saddr) saddr, a 2 4 (saddr) ? a a, sfr 2 4 a ? sfr sfr, a 2 4 sfr ? a a, !addr16 3 8 a ? (addr16) !addr16, a 3 8 (addr16) ? a psw, #byte 3 6 psw ? byte a, psw 2 4 a ? psw psw, a 2 4 psw ? a a, [de] 1 6 a ? (de) [de], a 1 6 (de) ? a a, [hl] 1 6 a ? (hl) [hl], a 1 6 (hl) ? a a, [hl + byte] 2 6 a ? (hl + byte) [hl + byte], a 2 6 (hl + byte) ? a xch a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? (sfr) a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) a, [hl + byte] 2 8 a ? (hl + byte) movw rp, #word 3 6 rp ? word ax, saddrp 2 6 ax ? (saddrp) saddrp, ax 2 8 (saddrp) ? ax ax, rp note 3 1 4 ax ? rp rp, ax note 3 1 4 rp ? ax notes 1. except when r = a. 2. except when r = a or x. 3. only when rp = bc, de, or hl. remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock controller register (pcc).
preliminary product information 114 m m m m pd789166y, 789167y, 789176y, 789177y mnemonic operand byte clock operation flag zaccy xchw ax, rp note 1 8 ax ? rp add a, #byte 2 4 a, cy ? a + byte saddr, #byte 3 6 (saddr), cy ? (saddr) + byte a, r 2 4 a, cy ? a + r a, saddr 2 4 a, cy ? a + (saddr) a, !addr16 3 8 a, cy ? a + (addr16) a, [hl] 1 6 a, cy ? a + (hl) a, [hl + byte] 2 6 a, cy ? a + (hl + byte) addc a, #byte 2 4 a, cy ? a + byte + cy saddr, #byte 3 6 (saddr), cy ? (saddr) + byte + cy a, r 2 4 a, cy ? a + r + cy a, saddr 2 4 a, cy ? a + (saddr) + cy a, !addr16 3 8 a, cy ? a + (addr16) + cy a, [hl] 1 6 a, cy ? a + (hl) + cy a, [hl + byte] 2 6 a, cy ? a + (hl + byte) + cy sub a, #byte 2 4 a, cy ? a - byte saddr, #byte 3 6 (saddr), cy ? (saddr) - byte a, r 2 4 a, cy ? a - r a, saddr 2 4 a, cy ? a - (saddr) a, !addr16 3 8 a, cy ? a - (addr16) a, [hl] 1 6 a, cy ? a - (hl) a, [hl + byte] 2 6 a, cy ? a - (hl + byte) subc a, #byte 2 4 a, cy ? a - byte - cy saddr, #byte 3 6 (saddr), cy ? (saddr) - byte - cy a, r 2 4 a, cy ? a - r - cy a, saddr 2 4 a, cy ? a - (saddr) - cy a, !addr16 3 8 a, cy ? a - (addr16) - cy a, [hl] 1 6 a, cy ? a - (hl) - cy a, [hl + byte] 2 6 a, cy ? a - (hl + byte) - cy and a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) note only when rp = bc, de, or hl. remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock controller register (pcc).
preliminary product information 115 m m m m pd789166y, 789167y, 789176y, 789177y mnemonic operand byte clock operation flag zaccy or a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) xor a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) cmp a, #byte 2 4 a - byte saddr, #byte 3 6 (saddr) - byte a, r 2 4 a - r a, saddr 2 4 a - (saddr) a, !addr16 3 8 a - (addr16) a, [hl] 1 6 a - (hl) a, [hl + byte] 2 6 a - (hl + byte) addw ax, #word 3 6 ax, cy ? ax + word subw ax, #word 3 6 ax, cy ? ax - word cmpw ax, #word 3 6 ax - word inc r 2 4 r ? r + 1 saddr 2 4 (saddr) ? (saddr) + 1 dec r 2 4 r ? r - 1 saddr 2 4 (saddr) ? (saddr) - 1 incw rp 1 4 rp ? rp + 1 decw rp 1 4 rp ? rp - 1 ror a, 1 1 2 (cy, a 7 ? a 0 , a m - 1 ? a m ) 1 rol a, 1 1 2 (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a, 1 1 2 (cy ? a 0 , a 7 ? cy, a m - 1 ? a m ) 1 rolc a, 1 1 2 (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock controller register (pcc).
preliminary product information 116 m m m m pd789166y, 789167y, 789176y, 789177y mnemonic operand byte clock operation flag zaccy set1 saddr. bit 3 6 (saddr. bit) ? 1 sfr. bit 3 6 sfr. bit ? 1 a. bit 2 4 a. bit ? 1 psw. bit 3 6 psw. bit ? 1 [hl]. bit 2 10 (hl). bit ? 1 clr1 saddr. bit 3 6 (saddr. bit) ? 0 sfr. bit 3 6 sfr. bit ? 0 a. bit 2 4 a. bit ? 0 psw. bit 3 6 psw. bit ? 0 [hl]. bit 2 10 (hl). bit ? 0 set1 cy 1 2 cy ? 11 clr1 cy 1 2 cy ? 00 not1 cy 1 2 cy ? cy call !addr16 3 6 (sp - 1) ? (pc + 3) h , (sp - 2) ? (pc + 3) l , pc ? addr16, sp ? sp - 2 callt [addr5] 1 8 (sp - 1) ? (pc + 1) h , (sp - 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp - 2 ret 1 6 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 8 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3, nmis ? 0 rrr push psw 1 2 (sp - 1) ? psw, sp ? sp - 1 rp 1 4 (sp - 1) ? rp h , (sp - 2) ? rp l , sp ? sp - 2 pop psw 1 4 psw ? (sp), sp ? sp + 1 r r r rp 1 6 rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 movw sp, ax 2 8 sp ? ax ax, sp 2 6 ax ? sp br !addr16 3 6 pc ? addr16 $addr16 2 6 pc ? pc + 2 + jdisp8 ax 1 6 pc h ? a, pc l ? x remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock controller register (pcc).
preliminary product information 117 m m m m pd789166y, 789167y, 789176y, 789177y mnemonic operand byte clock operation flag zaccy bc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 0 bt saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 1 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 1 psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 1 bf saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 0 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 0 psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 0 dbnz b, $addr16 2 6 b ? b - 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 c ? c - 1, then pc ? pc + 2 + jdisp8 if c 1 0 saddr, $addr16 3 8 (saddr) ? (saddr) - 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 nop 1 2 no operation ei 3 6 ie ? 1 (enable interrupt) di 3 6 ie ? 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock controller register (pcc).
preliminary product information 118 m m m m pd789166y, 789167y, 789176y, 789177y 11. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol conditions rated value unit supply voltage v dd - 0.3 to +7.0 v input voltage v i1 pins other than those for port 5 - 0.3 to v dd + 0.3 v v i2 p50 to p53 n-ch open drain - 0.3 to +13 v output voltage v o - 0.3 to v dd + 0.3 v high-level output current i oh each pin - 10 ma total for all pins - 30 ma low-level output current i ol each pin 30 ma total for all pins 160 ma operating ambient temperature t a - 40 to +85 c storage temperature t stg - 65 to +150 c caution absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. always use the product within its rated values. remark the characteristic of a dual-function pin does not differ between the port function and the secondary function, unless otherwise stated.
preliminary product information 119 m m m m pd789166y, 789167y, 789176y, 789177y characteristics of the main system clock oscillation circuit (t a = - - - - 40 c to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator oscillator frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz oscillation settling time notes 2, 3 reset by reset 2 15 /f x 4ms reset by an interrupt note 4 crystal oscillator frequency (f x ) note 1 1.0 5.0 mhz oscillation settling time note 2 v dd = 4.5 to 5.5 v 10 ms 30 external clock x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 input high/low level width (t xh , t xl ) 85 500 ns notes 1. only the characteristic of the oscillation circuit is indicated. see the description of the ac characteristic for the instruction execution time. 2. time required for oscillation to settle once a reset sequence ends or stop mode is deselected. 3. time after v dd reaches min. of the oscillation voltage range. 4. bits 0 to 2 (osts0 to osts2) of the oscillation settling time selection register can be used to select 2 12 /f x , 2 15 /f x , or 2 17 /f x . cautions 1. when using the main system clock oscillation circuit, observe the following conditions for the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the influence of the wiring capacitance. keep the wiring as short as possible. do not allow signal wires to cross one another. keep the wiring away from wires that carry a high, non-stable current. keep the grounding point of the capacitors at the same level as v ss . do not connect the grounding point to a grounding wire that carries a high current. do not extract a signal from the oscillation circuit. 2. before switching from the subsystem clock back to the main system clock, always allow sufficient time for the oscillation to settle by specifying it in the program. x1 x2 c2 c1 x1 x2 c2 c1 x1 x2
preliminary product information 120 m m m m pd789166y, 789167y, 789176y, 789177y characteristics of the subsystem clock oscillation circuit (t a = - - - - 40 c to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal oscillator frequency (f xt ) note 1 32 32.768 35 khz oscillation settling time note 2 v dd = 4.5 to 5.5 v 1.2 2 s 10 external clock xt1 input frequency (f xt ) note 1 32 35 khz xt1 input high/low level width (t xth , t xtl ) 14.3 15.6 m s notes 1. only the characteristic of the oscillation circuit is indicated. see the description of the ac characteristic for the instruction execution time. 2. time required for oscillation to settle after v dd reaches the min. value of the oscillation voltage range. cautions 1. when using the subsystem clock oscillation circuit, observe the following conditions for the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the influence of the wiring capacitance. keep the wiring as short as possible. do not allow signal wires to cross one another. keep the wiring away from wires that carry a high, non-stable current. keep the grounding point of the capacitors at the same level as v ss . do not connect the grounding point to a grounding wire that carries a high current. do not extract a signal from the oscillation circuit. 2. the subsystem clock oscillation circuit is designed to have a low amplification degree so as to maintain a low current drain. therefore, it is more likely to malfunction as a result of noise than the main system clock oscillation circuit. when using the subsystem clock, therefore, pay particularly careful attention to how it is wired. xt1 xt2 r c3 c4 xt1 xt2
preliminary product information 121 m m m m pd789166y, 789167y, 789176y, 789177y dc characteristics (t a = - - - - 40 c to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit i ol each pin undefined ma all pins 80 ma i oh each pin undefined ma all pins - 15 ma v ih1 p00 to p05, p10, p11, v dd = 2.7 to 5.5 v 0.7v dd v dd v p60 to p67 0.9v dd v dd v v ih2 p50 to p53 v dd = 2.7 to 5.5 v 0.7v dd 12 v 0.9v dd 12 v v ih3 reset, v dd = 2.7 to 5.5 v 0.8v dd v dd v p20 to p26, p30 to p33 0.9v dd v dd v v ih4 x1, x2 v dd - 0.1 v dd v v il1 p00 to p05, p10, p11, v dd = 2.7 to 5.5 v 0 0.3v dd v p60 to p67 0 0.1v dd v v il2 p50 to p53 v dd = 2.7 to 5.5 v 0 0.3v dd v 0 0.1v dd v v il3 reset, v dd = 2.7 to 5.5 v 0 0.2v dd v p20 to p26, p30 to p33 0 0.1v dd v v il4 x1, x2 0 0.1 v v oh v dd = 4.5 to 5.5 v, i oh = - 1 ma v dd - 1.0 v v dd = 1.8 to 5.5 v, i oh = - 100 m a v dd - 0.5 v v ol1 pins other than those for port 5 v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v v dd = 1.8 to 5.5 v, i ol = 400 m a 0.5 v v ol2 p50 to p53 v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v l lih1 v in = v dd pins other than the x1 pin, x2 pin, or those for port 5 3 m a l lih2 x1, x2 20 m a l lih3 v in = 12 v p50 to p53 (n-ch open drain) 20 m a l lil1 v in = 0 v pins other than the x1 pin, x2 pin, or those for port 5 - 3 m a l lil2 x1, x2 - 20 m a l lil3 p50 to p53 (n-ch open drain) during input instruction execution - 30 m a remark the characteristic of a dual-function pin does not differ between the port function and the secondary function, unless otherwise stated. low-level output current high-level output current high-level input voltage low-level input voltage high-level output voltage low-level output voltage high-level input leakage current low-level input leakage current p00 to p05, p10, p11, p20 to p22, p25, p26, p30 to p33
preliminary product information 122 m m m m pd789166y, 789167y, 789176y, 789177y dc characteristics (t a = - - - - 40 c to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit high-level output leakage current i loh v out = v dd 3 m a low-level output leakage current i lol v out = 0 v - 3 m a software-specified pull-up resistor r 1 v in = 0 v, for pins other than those for p23, p24, and p50 to p53 50 100 200 k w mask option- specified pull-up resistor r 2 v in = 0 v, p50 to p53 15 30 60 k w i dd1 v dd = 5.0 v 10% note 3 5.5 16.5 ma v dd = 3.0 v 10% 0.7 2.1 ma v dd = 2.0 v 10% 0.4 1.2 ma i dd2 v dd = 5.0 v 10% 1.2 3.6 ma v dd = 3.0 v 10% 0.5 1.5 ma v dd = 2.0 v 10% 0.3 0.9 ma i dd3 v dd = 5.0 v 10% 100 200 m a v dd = 3.0 v 10% 70 140 m a v dd = 2.0 v 10% 50 100 m a i dd4 v dd = 5.0 v 10% 25 55 m a v dd = 3.0 v 10% 525 m a v dd = 2.0 v 10% 2.5 12.5 m a i dd5 v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a v dd = 2.0 v 10% 0.05 10 m a i dd6 v dd = 5.0 v 10% 6.1 18.3 ma v dd = 3.0 v 10% 1.3 2.9 ma v dd = 2.0 v 10% 1.0 3.0 ma notes 1. the power supply current does not include av ref , av dd , or the port current (including the current flowing through the built-in pull-up resistor). 2. when the main system clock is not running. 3. during high-speed mode operation (when the processor clock control register (pcc) is cleared to 00h.) remark the characteristic of a dual-function pin does not differ between the port function and the secondary function, unless otherwise stated. power supply current note 1 5.0-mhz crystal oscillation operating mode 5.0-mhz crystal oscillation halt mode 32.768-khz crystal oscillation operating mode note 2 32.768-khz crystal oscillation halt mode note 2 32.768-khz crystal stop stop mode 5.0-mhz crystal oscillation a/d operating mode
preliminary product information 123 m m m m pd789166y, 789167y, 789176y, 789177y operation based on the main system clock ac characteristics (1) basic operations (t a = - - - - 40 c to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit t cy v dd = 2.7 to 5.5 v 0.4 8 m s 1.6 8 m s operation based on the subsystem clock 122 m s t tih , t til v dd = 2.7 to 5.5 v 0.1 m s 1.8 m s f ti v dd = 2.7 to 5.5 v 0 4 mhz 0 275 khz t inth , t intl intp0 to intp3 v dd = 2.7 to 5.5 v 10 m s 20 m s t rsl v dd = 2.7 to 5.5 v 10 m s 20 m s t cy vs v dd (main system clock) supply voltage v dd [v] 123456 0.1 0.4 0.5 1.0 2.0 10 60 cycle time t cy [ s] guaranteed operating range m cycle time (minimum instruction execution time) ti80 and ti81 input high/low level width ti80 and ti81 input frequency interrupt input high/low level width reset low level width
preliminary product information 124 m m m m pd789166y, 789167y, 789176y, 789177y serial interface (t a = - - - - 40 c to +85 c, v dd = 1.8 to 5.5 v) (a) serial interface 20 (i) three-wire serial i/o mode (sck...internal clock output) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 800 ns 3,200 ns t kh1 , t kl1 v dd = 2.7 to 5.5 v t kcy1 /2 - 50 ns t kcy1 /2 - 150 ns t sik1 v dd = 2.7 to 5.5 v 150 ns 500 ns t ksi1 v dd = 2.7 to 5.5 v 400 ns 600 ns t kso1 v dd = 2.7 to 5.5 v 0 250 ns 0 1,000 ns note r and c are the resistance and capacitance of the so output line, respectively. (ii) three-wire serial i/o mode (sck...external clock output) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3,200 ns t kh2 , t kl2 v dd = 2.7 to 5.5 v 400 ns 1,600 ns t sik2 v dd = 2.7 to 5.5 v 100 ns 150 ns t ksi2 v dd = 2.7 to 5.5 v 400 ns 600 ns t kso2 v dd = 2.7 to 5.5 v 0 300 ns 0 1,000 ns note r and c are the resistance and capacitance of the so output line, respectively. (iii) uart mode (internal clock output) parameter symbol conditions min. typ. max. unit transfer rate v dd = 2.7 to 5.5 v 78,125 bps 19,531 bps sck high/low level width si setup time (for sck - ) si hold time (for sck - ) delay from sck to so output sck high/low level width si setup time (for sck - ) si hold time (for sck - ) delay from sck to so output r = 1 k w , c = 100 pf note r = 1 k w , c = 100 pf note
preliminary product information 125 m m m m pd789166y, 789167y, 789176y, 789177y (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck cycle time t kcy3 v dd = 2.7 to 5.5 v 800 ns 3,200 ns t kh3 , t kl3 v dd = 2.7 to 5.5 v 400 ns 1,600 ns transfer rate v dd = 2.7 to 5.5 v 39,063 bps 9,766 bps t r , t f 1 m s (b) smb0 (i) dc characteristics parameter symbol conditions min. typ. max. unit v ih scl0, sda0 2.7 v v dd < 5.5 v 0.8v dd v dd v (during hysteresis) 0.9v dd v dd v v il scl0, sda0 2.7 v v dd < 5.5 v 0 0.2v dd v (during hysteresis) 0 0.1 v low-level output voltage v ol scl0, sda0 4.5 v v dd < 5.5 v i ol = 10 ma 1.0 v i ol = 400 m a 0.5 v high-level input leakage current i lih scl0, sda0 v in = v dd 3 m a low-level input leakage current i lil scl0, sda0 v in = 0 v - 3 m a (ii) dc characteristics (when the comparator is used) parameter symbol conditions min. typ. max. unit input range v sda , v scl 1.8 v v dd < 5.5 v 0 5.5 v transfer level vi sda , vi scl 0.6 1.0 1.4 v asck high/low level width asck rising time, falling time high-level input voltage low-level input voltage
preliminary product information 126 m m m m pd789166y, 789167y, 789176y, 789177y (iii) ac characteristics parameter symbol smb mode i 2 c standard mode i 2 c high-speed mode unit min. max. min. max. min. max. scl0 clock frequency f clk 10 100 0 100 0 400 khz bus free time (between stop-start conditions) t buf 4.7 - 4.7 - 1.3 - m s hold time note 1 t hd:sta 4.0 - 4.0 - 0.6 - m s start/restart condition setup time t su:sta 4.7 - 4.7 - 0.6 - m s stop condition setup time t su:sto 4.0 - 4.0 - 0.6 - m s data hold time cbus-compatible master t hd:dat - 500 --- m s smb/iic 300 -- 0 note 2 900 note 3 ns data setup time t su:dat 250 - 250 - 100 note 4 - ns scl0 clock low level width t low 4.7 - 4.7 - 1.3 - m s scl0 clock high level width t high 4.0 50 4.0 - 0.6 m s scl0 and sda0 signal falling time t f - 300 - 300 - 300 ns scl0 and sda0 signal rising time t r - 1,000 - 1,000 - 300 ns pulse width of spikes controlled by the input filter t sp 050ns time-out time t timeout 25 35 ---- ms scl0 clock low level period total extension time (slave) t low:sext - 25 ---- ms cumulative scl0 clock low level period total extension time (master) t low:mext - 10 ---- ms capacitive load of each bus line c b --- 400 - 400 pf notes 1. in the start condition, the first clock pulse is generated after this period of time. 2. to fill the undefined area of the scl0 falling edge (at v ihmin. of the scl0 signal), the device needs to internally provide a hold time of at least 300 ns for the sda0 signal. 3. if the device does not extend the low hold time (t low ) of the scl0 signal, the maximum data hold time (t hd:dat ) only needs to be satisfied. 4. i 2 c high-speed mode can be used in smb mode and i 2 c standard mode. in this case, the following conditions must be satisfied: when the device does not extend the low hold time of the scl0 signal t su:dat 3 250 ns when the device extends the low hold time of the scl0 signal before scl0 is released (t rmax. + t su:dat = 1,000 + 250 = 1,250 ns: in smb mode or i 2 c standard mode), the next data bit must be sent onto the sda0 line.
preliminary product information 127 m m m m pd789166y, 789167y, 789176y, 789177y ac timing measurement points (except the x1 and xt1 inputs) 0.8v dd 0.2v dd measurement points 0.8v dd 0.2v dd clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih5 (min.) v il5 (max.) ti timing t tih0 , t tih1 t til0 , t til1 ti80, ti81
preliminary product information 128 m m m m pd789166y, 789167y, 789176y, 789177y interrupt input timing intp0-intp3 t intl t inth reset input timing reset t rsl
preliminary product information 129 m m m m pd789166y, 789167y, 789176y, 789177y serial transfer timing three-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data output data t ksom so20 ss20 so20 t kas t kds m = 1, 2 uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
preliminary product information 130 m m m m pd789166y, 789167y, 789176y, 789177y smb mode: scl0 sda0 t hd:sta t buf t hd:dat t high t f t su:dat t su:sta t hd:sta t sp t su : sto t r t low stop condition start condition stop condition restart condition
preliminary product information 131 m m m m pd789166y, 789167y, 789176y, 789177y 8-bit a/d converter characteristics (t a = - - - - 40 c to +85 c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) (for m pd789166y and m pd789167y only) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit total error note 4.5 v av dd 5.5 v 0.5 1 lsb 2.7 v av dd < 4.5 v 1 1.75 lsb 1.8 v av dd < 2.7 v undefined undefined lsb conversion time t conv 4.5 v av dd 5.5 v undefined undefined m s 2.7 v av dd < 4.5 v undefined undefined m s 1.8 v av dd < 2.7 v undefined undefined m s analog input voltage v ian 0av ref + 0.3 v reference voltage av ref 0av dd + 0.3 v note no quantization error ( 1/2 lsb) is included. 10-bit a/d converter characteristics (t a = - - - - 40 c to +85 c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) (for m pd789176y and m PD789177Y only) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit total error note 4.5 v av dd 5.5 v 2 4 lsb 2.7 v av dd < 4.5 v 4 7 lsb 1.8 v av dd < 2.7 v undefined undefined lsb conversion time t conv 4.5 v av dd 5.5 v undefined undefined m s 2.7 v av dd < 4.5 v undefined undefined m s 1.8 v av dd < 2.7 v undefined undefined m s analog input voltage v ian 0av ref + 0.3 v reference voltage av ref 0av dd + 0.3 v note no quantization error ( 1/2 lsb) is included. data memory stop mode low power supply voltage data hold characteristics (t a = - - - - 40 c to +85 c) parameter symbol conditions min. typ. max. unit data hold supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 m s
preliminary product information 132 m m m m pd789166y, 789167y, 789176y, 789177y data hold timing (stop mode release by reset) v dd data hold mode stop mode internal reset operation t srel stop instruction execution v dddr reset
preliminary product information 133 m m m m pd789166y, 789167y, 789176y, 789177y 12. package drawings 42pin plastic shrink dip (600 mil) item millimeters inches a b c f g h i j k 39.13 max. 1.778 (t.p.) 3.2 0.3 0.51 min. 4.31 max. 1.78 max. 0.17 15.24 (t.p.) 5.08 max. n 0.9 min. r 1.541 max. 0.070 max. 0.035 min. 0.126 0.012 0.020 min. 0.170 max. 0.200 max. 0.600 (t.p.) 0.007 0.070 (t.p.) p42c-70-600a-1 a c d g notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. d 0.50 0.10 0.020 m 0.25 0.010 +0.10 ?.05 0~15 0~15 +0.004 ?.003 +0.004 ?.005 m k n l 13.2 0.520 2) item "k" to center of leads when formed parallel. 42 1 22 21 l m r b f h j i
preliminary product information 134 m m m m pd789166y, 789167y, 789176y, 789177y 44 pin plastic qfp ( 10) s44gb-80-3bs-1 item millimeters inches n q 0.125 0.075 0.10 0.004 0.005 0.003 j i h n a 13.2 0.2 0.520 +0.008 ?.009 b 10.0 0.2 0.394 +0.008 ?.009 c 10.0 0.2 0.394 +0.008 ?.009 d 13.2 0.2 0.520 +0.008 ?.009 f g h 1.0 0.37 1.0 0.039 0.039 0.015 +0.003 ?.004 i j k 0.8 (t.p.) 1.6 0.2 0.16 0.007 0.031 (t.p.) 0.063 0.008 l 0.8 0.2 0.031 +0.009 ?.008 m 0.17 0.007 +0.002 ?.003 s 3.0 max. 0.119 max. r3 3 +7 ? +0.08 ?.07 +0.06 ?.05 +7 ? detail of lead end q f g k m l r m s p p 2.7 0.1 0.106 +0.005 ?.004 note 1. controlling dimension millimeter. 2. each lead centerline is located within 0.16 mm (0.007 inch) of its true position (t.p.) at maximum material condition. 33 34 22 44 1 12 11 23 s s a b cd
preliminary product information 135 m m m m pd789166y, 789167y, 789176y, 789177y 48 pin plastic tqfp (fine pitch) ( 7) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 9.0 0.2 0.354 +0.009 ?.008 b 7.0 0.2 0.276 +0.008 ?.009 c 7.0 0.2 0.276 +0.008 ?.009 d 9.0 0.2 0.354 +0.009 ?.008 f g 0.75 0.75 0.030 0.030 h 0.22 0.009 0.002 s48ga-50-9eu-1 s 1.27 max. 0.050 max. k 1.0 0.2 0.039 +0.009 ?.008 l 0.5 0.2 0.020 +0.008 ?.009 m 0.145 0.006 0.002 n 0.10 0.004 p 1.0 0.1 0.039 +0.005 ?.004 q 0.1 0.05 0.004 0.002 +0.05 ?.04 +0.055 ?.045 b c d j h i g f p n l k m q r m 36 37 24 48 1 13 12 25 r3 3 +7 ? +7 ? detail of lead end
preliminary product information 136 m m m m pd789166y, 789167y, 789176y, 789177y appendix a development tools the following development tools are available for developing systems using the m pd789166y, m pd789167y, m pd789176y, and m PD789177Y. language processing software ra78k0s notes 1, 2, 3 assembler package common to the 78k/0s series cc78k0s notes 1, 2, 3 c compiler package common to the 78k/0s series df789177 notes 1, 2, 3, 5 device file for the m pd789167y and m PD789177Y sub-series cc78k0s-l notes 1, 2, 3, 5 c compiler library source file common to the 78k/0s series flash memory write tools flashpro ll note 4 dedicated flash writer (formerly, flashpro) fa-42cu note 4 flash memory write adapter fa-44gb note 4 fa-48ga notes 4, 5 debugging tools ie-78k0s-ns in-circuit emulator this in-circuit emulator is used to debug hardware or software when application systems which use the 78k/0s series are devel oped. the ie-78k0s-ns supports the integrated debugger (id78k0s-ns). the ie-78k0s-ns is used in combination with an interface adapter for connection to an ac adapter, emulation probe, or host machine. ie-70000-mc-ps-b ac adapter this adapter is used to supply power from a 100-vac outlet. ie-70000-98-if-c interface adapter this adapter is required when a pc-9800 series computer (other than a notebook type) is used as the host machine for the ie-78k0s-ns. ie-70000-cd-if pc card/interface these pc card and interface cable are required when a pc-9800 series computer is used as the host machine for the ie-78k0s-ns. ie-70000-pc-if-c interface adapter this adapter is required when an ibm pc/at or compatible is used as the host machine for the ie-78k0s-ns. ie-789177-ns-em1 note 5 emulation board this board is used to emulate the peripheral hardware specific to the device. the ie-789198-ns-em1 is used in combination with the in-circuit emulator. np-42cu note 4 emulation probe this probe is used to connect an in-circuit emulator to the target system. the pr obe is dedicated to the 42-pin plastic shrink dip. np-44gb note 4 emulation probe this probe is used to connect an in-circuit emulator to the target system. the pr obe is dedicated to the 44-pin plastic qfp. np-48ga notes 4, 5 emulation probe this probe is used to connect an in-circuit emulator to the target system. the pr obe is dedicated to the 48-pin plastic tqfp. sm78k0s notes 1, 2 system simulator common to all 78k/0s series units df789177 notes 1, 2, 5 device file for the m pd789167y and m PD789177Y sub-series
preliminary product information 137 m m m m pd789166y, 789167y, 789176y, 789177y real-time os mx78k0s notes 1, 2, 5 os for the 78k/0s series notes 1. based on the pc-9800 series (ms-dos ? + windows ? ) 2. based on the ibm pc/at ? and compatibles (pc dos ? /ibm dos ? /ms-dos + windows) 3. based on the hp9000 series 700 ? (hp-ux ? ), sparcstation ? (sunos ? ), and news ? (news-os ? ) 4. product manufactured by and available from naito densei machida mfg. co., ltd. (044-822-3813). 5. under development remark the ra78k0s, cc78k0s, and sm78k0s can be used in combination with the df789177.
preliminary product information 138 m m m m pd789166y, 789167y, 789176y, 789177y appendix b related documents documents related to devices document name document no. japanese english m pd789166y, 789167y, 789176y, 789177y preliminary product information u13216j this manual m pd78f9177y preliminary product information u13210j to be created m PD789177Y sub-series users manual to be created to be created 78k/0 series users manual, instruction u11047j u11047e 78k/0s series instruction summary sheet to be created - 78k/0s series instruction set to be created - documents related to development tools (users manual) document name document no. japanese english ra78k0s assembler package operation u11622j u11622e language u11599j u11599e structured assembly language u11623j u11623e cc78k/0s c compiler operation u11816j u11816e language u11817j u11817e sm78k0s system simulator windows base reference u11489j u11489e sm78k series system simulator external parts user open interface specifications u10092j u10092e id78k0s-ns windows base reference u12901j to be created documents related to software to be incorporated into the product (users manual) document name document no. japanese english os for 78k/0s series mx78k0s fundamental u12938j u12938e caution the above documents may be revised without notice. use the latest versions when you design application systems.
preliminary product information 139 m m m m pd789166y, 789167y, 789176y, 789177y other documents document name document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e semiconductor device quality control/reliability handbook c12769j - guide for products related to microcomputer: other companies u11416j - caution the above documents may be revised without notice. use the latest versions when you design application systems.
preliminary product information 140 m m m m pd789166y, 789167y, 789176y, 789177y notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
preliminary product information 141 m m m m pd789166y, 789167y, 789176y, 789177y eeprom is a trademark of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation.
preliminary product information 142 m m m m pd789166y, 789167y, 789176y, 789177y regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 j98. 2
preliminary product information 143 m m m m pd789166y, 789167y, 789176y, 789177y [memo]
m m m m pd789166y, 789167y, 789176y, 789177y the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. caution this product contains an i 2 c bus interface circuit. when using the i 2 c bus interface, notify its use to nec when ordering custom code. nec can guarantee the following only when the customer informs nec of the use of the interface: purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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